EP7309-CBZ Cirrus Logic Inc, EP7309-CBZ Datasheet - Page 18
![IC ARM720T MCU 74MHZ 256-PBGA](/photos/12/32/123256/mfg_ep7309_parts_sml.jpg)
EP7309-CBZ
Manufacturer Part Number
EP7309-CBZ
Description
IC ARM720T MCU 74MHZ 256-PBGA
Manufacturer
Cirrus Logic Inc
Series
EP7r
Specifications of EP7309-CBZ
Core Size
32-Bit
Core Processor
ARM7
Speed
74MHz
Connectivity
Codec, DAI, EBI/EMI, IrDA, Keypad, SPI/Microwire1, UART/USART
Peripherals
LCD, LED, MaverickKey, POR, PWM
Number Of I /o
27
Program Memory Type
ROMless
Ram Size
56K x 8
Voltage - Supply (vcc/vdd)
2.3 V ~ 2.7 V
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
256-BGA
Controller Family/series
(ARM7)
No. Of I/o's
27
Ram Memory Size
48KB
Cpu Speed
74MHz
No. Of Timers
2
No. Of Pwm Channels
2
Digital Ic Case Style
BGA
Embedded Interface Type
SSI, UART
Rohs Compliant
Yes
Processor Series
EP73xx
Core
ARM720T
Data Bus Width
32 bit
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Other names
598-1211
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
EP7309
High-Performance, Low-Power System on Chip
Static Memory Burst Read Cycle
18
EXPRDY
EXPCLK
W RITE
W ORD
W ORD
nM W E
nM OE
HALF
nCS
A
D
Note: 1. Four cycles are shown in the above diagram (minimum wait states, 1-0-0-0). This is the maximum number of consecutive
cycles that can be driven. The number of consecutive cycles can be programmed from 2 to 4, inclusively.
2. The cycle time can be extended by integer multiples of the clock period (22 ns at 45 MHz, 27 ns at 36 MHz, 54 ns at
18.432 MHz, and 77 ns at 13 MHz), by either driving EXPRDY low and/or by programming a number of wait states. EXPRDY is
sampled on the falling edge of EXPCLK before the data transfer. If low at this point, the transfer is delayed by one clock period
where EXPRDY is sampled again. EXPCLK need not be referenced when driving EXPRDY, but is shown for clarity.
3. Consecutive reads with sequential access enabled are identical except that the sequential access wait state field is used to
determine the number of wait states, and no idle cycles are inserted between successive non-sequential ROM/expansion
cycles. This improves performance so the SQAEN bit should always be set where possible.
4. Address, Halfword, Word, and Write hold state until next cycle.
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Figure 5. Static Memory Burst Read Cycle Timing Measurement
EXs
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EXh
Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved)
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