EP9307-IRZ Cirrus Logic Inc, EP9307-IRZ Datasheet
EP9307-IRZ
Specifications of EP9307-IRZ
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EP9307-IRZ Summary of contents
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... Errata: EP9307 - Silicon Revision: E2 Reference EP9307 Data Sheet revision DS667PP4 dated March 2005. Determining the Silicon Revision of the Integrated Circuit On the front of the integrated circuit, directly under the part number alpha-numeric line. Characters 5 and 6 in this line represent the silicon revision of the chip. For example, this line indicates that the chip is a “ ...
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Analog Touch Screen Description After power-on-reset, PENSTS in AR_SETUP2 register has the correct default value of “0”. But after the first touch on the screen, PENSTS is stuck at “1” regardless if the screen is pressed or not. Workaround Configure ...
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HDLC Description When the final byte of a received packet is read into the DMA controller's buffer, the software will be notified by an HDLC RFC interrupt. However, the DMA controller may not have written the currently buffered part of ...
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Raster EP9312 User's Guide Update As designed, horizontal clock and data are not aligned. Where horizontal clock gating is required, set HACTIVESTRTSTOP equal to HCLKSTRTSTOP+5. Description 1 If the raster engine is using single scan mode, two and two thirds ...
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USB Description 1 USB clock divider logic operates at a maximum rate of 288MHz under worst case conditions. Workaround When using USB, make sure the clock frequency supplied to the USB clock divider does not exceed 288MHz. The clock supplied ...
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TM MaverickCrunch Various MaverickCrunch errata share common features. The individual descriptions will refer to these common features. 1) For several errata, an instruction appears in the coprocessor pipeline, but does not execute for one of the following reasons ...
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Description 1 Under certain circumstances, data in coprocessor registers or in memory may be corrupted. The following sequence of instructions will cause the corruption: 1) Let the first instruction be both: - any coprocessor instruction that is not executed - ...
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Workaround The simplest workaround is to insure that no two such instructions ever appear in the instruction stream consecutively. Specifically, a conditional coprocessor instruction should not precede a load/store 64/double. Simply inserting another ARM or coprocessor instruction accomplishes this: cfaddne ...
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Workaround Insure that this kind of sequence of instructions does not occur. Note that adding a small number of intervening instructions may not be sufficient to avoid this problem. If such a sequence must occur, insure that the first and ...
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Workaround Separating the first and second instruction by one instruction will avoid this error whether or not the coprocessor is operating in serialized or unserialized mode. For example: cfadd32ne c0, c1, c2 nop cfldr64 c3, [r2, #0x0] cfadd32ne c4, c5, ...
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Note: The effect of branches should also be accounted for the instruction stream as seen by the coprocessor that matters, not the order of instructions in the source code. To avoid this error when entering exception and ...
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Description 7 The coprocessor can incorrectly update one of its destination accumulators even if the coprocessor instruction should not have been executed or is canceled by the ARM processor. This error can occur if the following is true: 1) The ...
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Workaround A complete software workaround requires ensuring that data aborts do not occur due to any instruction immediately preceding a coprocessor instruction that writes to an accumulator. The only way to ensure this is to not allow memory operations immediately ...
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Description 11 An erroneous memory transfer to or from any of the coprocessor general purpose registers c0 through c15 can occur given the following conditions are satisfied: 1) The first instruction two-word load or store - fails ...
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Description 12 When an operand to the Crunch add/subtract unit is denormalized forced to zero before input to the calculation. The sign is unaffected. This affects the following instructions: - Copies: cfcpys, cfcpyd - Add/Sub: cfadds, cfaddd, cfsubs, ...
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Revision History Errata Device Document Date Revision Revision E2 Initial Errata March 2005 E2 A April 2007 E2 A April 2007 E2 B April 2007 16 Revision History Functionality Summary of Errata Affected Processor may boot into an invalid state. ...