EP9312-IB Cirrus Logic Inc, EP9312-IB Datasheet - Page 55

• Manufacturer Part Number: EP9312-IB
• Description: IC ARM920T MCU 200MHZ 352-PBGA
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9312-IB

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 352-BGA
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No
• Other names: 598-1259

W P[12]
Y HSYNC
V
U AD[0]
R AD[2]
P
N DA[13]
M AD[7]
K AD[22]
H
G
E AD[23]
D AD[24]
C CSN[1] CSN[3] AD[20] DA[29]
B CSN[2] DA[31] DA[30] DA[27]
A CSN[7] DA[28] AD[18]
T
L DA[18]
J DA[21]
F
SDCSN[
SDCSN[
DQMN[
DA[8]
AD[4]
P[16]
3]
0]
3]
1
1
SDCSN[
BLANK
DQMN[
DA[10]
DA[12] DA[11]
DA[14]
DA[17] DA[16] DA[15]
DA[20] AD[21] DA[19]
DA[22] DA[24] AD[25]
DA[23] DA[26] CSN[6]
DA[25] DD[11]
CASN
DD[1]
AD[1]
P[11]
P[15]
P[9]
0]
1]
2
2
DQMN[
DD[12]
SDWE
RASN
DD[0]
DA[9] BRIGHT RVDD
AD[6]
P[10]
P[13]
P[17]
P[8]
1]
N
3
3
DQMN[2
SDCSN[
SPCLK
SDCLK
SDCLK
DD[15]
AD[3]
AD[5]
DD[8]
P[14]
P[2]
P[5]
P[7]
EN
2]
4
4
]
V_CSY
AD[15] DA[6] DA[4]
DD[13]
AD[19] DD[9] DD[5]
DD[10] DD[6] DD[2] MDC
RVDD
CVDD
CVDD
RVDD
CVDD
RVDD
RVDD GND
DD[7] DD[3] WRN MDIO
DD[4]
GND
GND
GND
P[3]
P[6]
NC
5
5
DA[7] DA[5]
DD[1
GND
AD[1
RVD
RVD
CVD
RVD
P[1]
P[4] P[0]
4]
7]
D
D
D
D
6
6
AD[1
GND
GND
CVD
CVD
RDN
4]
D
D
7
7
AD[10
AD[12
AD[13
AD[16
AD[11
RXCL
GND
GND
GND
GND
GND
GND
CVD
CVD
CVD
8
D
D
D
K
8
]
]
]
]
]
MIIRXD[
MIIRXD[
MIIRXD[
MIIRXD[
RVDD
RVDD
DA[1]
AD[9]
DA[2]
DA[3]
GND
GND
GND
GND
GND
GND
2]
3]
1]
0]
9
9
Figure 40. 352 PIN BGA PINOUT
MIITXD[
IDECS1
IDECS0
RXERR
RXDVA
TXCLK
AD[8]
DA[0]
GND
GND
GND
GND
GND
GND
GND
GND
10
10
N
N
3]
L
MIITXD[
MIITXD[
MIITXD[
IDEDA[
IDEDA[
IDEDA[
DSRN BOOT[1]
TXEN
GND
GND
GND
GND
GND
GND
GND
GND
11
11
0]
1]
2]
0]
1]
2]
TXERR
DTRN
RVDD
RVDD
GND
GND
GND
GND
GND
GND
CRS
TCK
TDI
NC
NC
12
12
CVDD
CVDD
CVDD
GND
GND
GND
GND
GND
GND
GND
TDO
TMS
CLD
NC
NC
NC
NC
13
13
BOOT[0] EEDAT
SSPRX1 INT[1]
ASYNC SSPTX1 INT[2]
EECLK
CVDD
CVDD
GND
GND
NC
NC
NC
NC
14
14
EGPIO[
SCLK1 GRLED
INT[0]
RVDD
RVDD
RVDD
GND
GND
GND
14]
NC
NC
NC
15
15
USBM[1
PWMO
ASDO
RVDD
RVDD
CVDD
CVDD
CVDD
RVDD
RVDD EGPIO[7]
ASDI
GND
GND
GND
UT
NC
NC
NC
NC
16
16
]
EGPIO[2]
USBM[0] RXD[1]
RTCXTA
RTCXTA
USBM[2] ARSTN DIORN EGPIO[1] D
EGPIO[1
EGPIO[1
ROW[0] ROW[3]
SFRM1 RDLED USBP[1] ABITCLK Y
DIOWN
RXD[0]
XTALO
COL[4]
COL[5]
INT[3]
RTSN
XTALI
SYM
LO
NC
17
17
LI
3]
2]
USBP[0] CTSN
PLL_VD
USBP[2] IORDY DMACKN C
ADC_V
EGPIO[
EGPIO[
EGPIO[
EGPIO[
COL[0]
COL[3]
COL[7] RSTON
SLA[1]
TXD[2] ROW[2]
SYP
XM
DD
NC
15]
18
18
D
9]
4]
0]
EGPIO[1
EGPIO[6
EGPIO[3
PLL_GN
ROW[6]
ADC_G
TXD[1]
COL[1]
COL[6]
WAITN
SLA[0]
SXM
YP
ND
NC
19
19
D
0]
]
]
EGPIO[11
EGPIO[8] F
EGPIO[5] E
ROW[1] U
ROW[4] T
ROW[5] R
ROW[7] P
RXD[2] W
CSN[0] M
PRSTN
TRSTN B
TXD[0]
COL[2]
SXP
YM
NC
XP
20
20
]
G
V
N
L
K
J
H
A