EP9312-IB Cirrus Logic Inc, EP9312-IB Datasheet - Page 7

• Manufacturer Part Number: EP9312-IB
• Description: IC ARM920T MCU 200MHZ 352-PBGA
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9312-IB

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 352-BGA
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No
• Other names: 598-1259

MaverickCrunch
ER515E2B
Erratum Failing Coprocessor Instructions
10.
11.
12.
13.
1.
2.
3.
4.
5.
6.
7.
8.
9.
Various MaverickCrunch errata share common features. The individual descriptions will refer to these
common features.
1) For several errata, an instruction appears in the coprocessor pipeline, but does not execute for one of
2) For several errata, the coprocessor must be either operating in serialized mode or not be operating in
3) For several errata, an instruction must update an accumulator. These include all of the following:
4) For several errata, an instruction must be any two-word coprocessor load or store. These include cfldr64,
The following table summarizes MaverickCrunch errata.
Several of the errata are sensitive to certain coprocessor instructions appearing early in an interrupt or
exception handler. To avoid seeing any errata due to such instructions, insure that no coprocessor
instructions appear in the instruction stream within the first seven instructions after an interrupt or exception.
Note that, typically, the first three instructions in this stream would be a branch in the jump table followed by
the two instructions in the branch delay slot.
two-word load / store
instruction with source operand
two-word load / store
two-word store
cfrshl32, cfrshl64
ldr32, mv64lr
accumulator updates
accumulator updates
accumulator updates
accumulator updates
two-word load / store
floating point add, cpy, abs, neg
cfcvtds
the following reasons:
serialized mode. The coprocessor is operating in serialized mode if and only if both:
cfldrd, cfstr64, and cfstrd.
- It fails its condition code check.
- A branch is taken and it is one of the two instructions in the branch delay slot.
- An exception occurs.
- An interrupt occurs.
- At least one exception type is enabled by setting one of the following bits in the DSPSC: IXE, UFE,
- Serialization is not specifically disabled by setting the AEXC bit in the DSPSC.
- Moves to accumulators: cfmva32, cfmva64, cfmval32, cfmvam32, cfmvah32.
- Arithmetic into accumulators: cfmadd32, cfmadda32, cfmsub32, cfmsuba32.
OFE, or IOE.
TM
not serialized
forwarding,
serialized
serialized
Mode
register or memory corruption
bad calculation or stored value change sequence
register or memory corruption
memory corruption
bad calculation
bad sign extension in register
accumulator corruption
accumulator corruption
accumulator corruption
accumulator corruption
memory or register corruption
denorm operand forced to
zero, cpy/neg never produces
+zero
never produces denorms
Result
change sequence
change sequence
change sequence
unserialized mode,
substitute ARM code sequence
add correcting code sequence
change sequence
change sequence
change sequence
unserialized mode
change sequence
none
none
Workaround
7