STM8S105C4T3 STMicroelectronics, STM8S105C4T3 Datasheet - Page 12
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STM8S105C4T3
Manufacturer Part Number
STM8S105C4T3
Description
MCU 8BIT 16K FLASH 48-LQFP
Manufacturer
STMicroelectronics
Series
STM8Sr
Datasheet
1.STM8S105C4T6.pdf
(127 pages)
Specifications of STM8S105C4T3
Core Processor
STM8
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
38
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.95 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-LQFP
Processor Series
STM8S10x
Core
STM8
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
I2C, UART, IrDA, LIN, SPI
Number Of Programmable I/os
38
Number Of Timers
7
Operating Supply Voltage
2.95 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWSTM8
Development Tools By Supplier
STICE-SYS001
Minimum Operating Temperature
- 40 C
Featured Product
STM32 Cortex-M3 Companion Products
For Use With
497-10040 - EVAL KIT STM8S DISCOVERY497-10593 - KIT STARTER FOR STM8S207/8 SER
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
STM8S105C4T3
Manufacturer:
ST
Quantity:
1 469
Company:
Part Number:
STM8S105C4T3
Manufacturer:
STMicroelectronics
Quantity:
10 000
Product overview
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4.2
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Product overview
The following section intends to give an overview of the basic features of the device functional
modules and peripherals.
For more detailed information please refer to the corresponding family reference manual
(RM0016).
Central processing unit STM8
The 8-bit STM8 core is designed for code efficiency and performance.
It contains 6 internal registers which are directly addressable in each execution context, 20
addressing modes including indexed indirect and relative addressing and 80 instructions.
Architecture and registers
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Addressing
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Instruction set
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Single wire interface module (SWIM) and debug module (DM)
The single wire interface module and debug module permits non-intrusive, real-time in-circuit
debugging and fast memory programming.
Harvard architecture
3-stage pipeline
32-bit wide program memory bus - single cycle fetching for most instructions
X and Y 16-bit index registers - enabling indexed addressing modes with or without offset
and read-modify-write type data manipulations
8-bit accumulator
24-bit program counter - 16-Mbyte linear memory space
16-bit stack pointer - access to a 64 K-level stack
8-bit condition code register - 7 condition flags for the result of the last instruction
20 addressing modes
Indexed indirect addressing mode for look-up tables located anywhere in the address
space
Stack pointer relative addressing mode for local variables and parameter passing
80 instructions with 2-byte average instruction size
Standard data movement and logic/arithmetic functions
8-bit by 8-bit multiplication
16-bit by 8-bit and 16-bit by 16-bit division
Bit manipulation
Data transfer between stack and accumulator (push/pop) with direct stack access
Data transfer using the X and Y registers or direct memory-to-memory transfers
DocID14771 Rev 10
STM8S105xx