EZ80F93AZ020SC00TR Zilog, EZ80F93AZ020SC00TR Datasheet - Page 53
![IC ACCLAIM MCU 64KB 100LQFP](/photos/6/76/67664/269-100-lqfp_sml.jpg)
EZ80F93AZ020SC00TR
Manufacturer Part Number
EZ80F93AZ020SC00TR
Description
IC ACCLAIM MCU 64KB 100LQFP
Manufacturer
Zilog
Series
eZ80® Acclaim!®r
Specifications of EZ80F93AZ020SC00TR
Core Processor
Z8
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
24
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Other names
EZ80F93AZ020SC00T
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Table 12. Vectored Interrupt Operation
PS015313-0508
Memory
Mode
Z80
ADL Mode
®
Mode 0
ADL
Bit
1
stored at {MBASE[7:0], I[7:0],
byte is stored at the lower address.
When any one or more of the interrupt requests (IRQs) become active, an interrupt request
is generated by the interrupt controller and sent to the CPU. The corresponding 8-bit inter-
rupt vector for the highest-priority interrupt is placed on the 8-bit interrupt vector bus,
IVECT[7:0]. The interrupt vector bus is internal to the eZ80F92 device and is therefore
not visible externally.
The response time of the CPU to an interrupt request is a function of the current instruc-
tion being executed as well as the number of wait states being asserted. The interrupt vec-
tor, {I[7:0], IVECT[7:0]}, is visible on the address bus, ADDR[15:0], when the interrupt
service routine begins. The response of the CPU to a vectored interrupt on the eZ80F92
device is listed in
service routine starts. It is recommended that the Interrupt Page Address Register (I) value
be changed by the user from its default value of
between the nonmaskable interrupt vector, the RST instruction addresses, and the
maskable interrupt vectors.
MADL
Bit
0
0
Operation
Read the LSB of the interrupt vector placed on the internal vectored
interrupt bus, IVECT [7:0], by the interrupting peripheral.
•
•
•
•
•
•
•
•
•
Read the LSB of the interrupt vector placed on the internal vectored
interrupt bus, IVECT [7:0], by the interrupting peripheral.
•
•
•
•
•
•
•
•
•
IEF1
IEF2
The Starting Program Counter is effectively {MBASE, PC[15:0]}
Push the 2-byte return address PC[15:0] onto the ({MBASE,SPS}) stack
The ADL mode bit remains cleared to 0
The interrupt vector address is located at {MBASE, I[7:0], IVECT[7:0]}
PC[15:0]
The ending Program Counter is effectively {MBASE, PC[15:0]}
The interrupt service routine must end with RETI
IEF1
IEF2
The Starting Program Counter is PC[23:0]
Push the 3-byte return address, PC[23:0], onto the SPL stack
The ADL mode bit remains set to 1
The interrupt vector address is located at {00h, I[7:0], IVECT[7:0]}
PC[15:0]
The ending Program Counter is {00h, PC[15:0]}
The interrupt service routine must end with RETI
Table
←
←
←
←
12. Interrupt sources are required to be active until the interrupt
0
0
0
0
←
←
({MBASE, I[7:0], IVECT[7:0]})
({00h, I[7:0], IVECT[7:0]})
1Eh
} and {MBASE, I[7:0],
00h
as this address can create conflicts
1Fh
}. The least-significant
Product Specification
eZ80F92/eZ80F93
Interrupt Controller
46
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