Z86C9620VSG Zilog, Z86C9620VSG Datasheet - Page 30

IC Z8 20MHZ C91 W/7 PORTS 68PLCC

Z86C9620VSG

Manufacturer Part Number
Z86C9620VSG
Description
IC Z8 20MHZ C91 W/7 PORTS 68PLCC
Manufacturer
Zilog
Series
Z8®r
Datasheet

Specifications of Z86C9620VSG

Core Processor
Z8
Core Size
8-Bit
Speed
20MHz
Connectivity
EBI/EMI, UART/USART
Number Of I /o
52
Program Memory Type
ROMless
Ram Size
236 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
68-PLCC
Processor Series
Z86C9xx
Core
Z8
Data Bus Width
8 bit
Program Memory Size
16 KB
Data Ram Size
236 B
Interface Type
UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
52
Number Of Timers
2
Operating Supply Voltage
3 V to 5.5 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Peripherals
-
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
Z86C9620VSG
Manufacturer:
Zilog
Quantity:
10 000
FUNCTIONAL DESCRIPTION (Continued)
Z86C61/62/96
CMOS Z8 Microcontroller
Expanded Register File. The register file has been ex-
panded to allow for additional system control registers,
and for mapping of additional peripheral devices along
with I/O ports into the register address area. The Z8 regis-
ter address space R0 through R15 has now been imple-
mented as 16 groups of 16 registers per group. These reg-
ister groups are known as the ERF (Expanded Register
File). Bits 7-4 of Register RP select the working register
group. Bits 3-0 of Register RP select the expanded register
group (Figure 21). Eight I/O port registers reside in the Ex-
panded Register File at Bank F. The rest of the Expanded
Register is not physically implemented and is open for fu-
ture expansion.
The upper nibble of the register pointer (Figure 20) selects
which group of 16 bytes in the register file, out of the full
236, will be accessed. The lower nibble selects the ex-
panded register file bank and in the case of the
Z86C61/62/96, only Bank F is implemented. A 0H in the
lower nibble will allow the normal register file to be ad-
dressed, but any other value from 1H to FH will exchange
the lower 16 registers in favor of an expanded register
group of 16 registers.
For example:
Z86C61: (See Figures 21 and 22)
But If:
30
R253 RP = 00H
R253 RP = 0FH
R0 = Port 0
R1 = Port 1
R0 = Reserved
R1 = Reserved
R2 = Port 4
R3 = Port 4, Direction Register
R9 = Port 6, Mode Register
R2 = Port 2
R3 = Port 3
PS003501-0301
P R E L I M I N A R Y
Further examples:
SRP #0FH
LD R2, #10010110
LD 2, #10010110
LD 9, #11110000
SRP #1FH
LD R2, #11010110
LD 12H, #11010110
LD 2, #10010110
RAM Protect. The upper portion of the RAM’s address
spaces 80FH to EFH (excluding the control registers) can
be protected from reading and writing. The RAM Protect bit
option is mask-programmable and is selected by the cus-
tomer when the ROM code is submitted. After the mask
option is selected, the user can activate from the internal
ROM code to turn off/on the RAM Protect by loading a bit
D6 in the IMR register to either a 0 or a 1, respectively. A
1 in D6 indicates RAM Protect enabled.
ROM Protect. The first 16 Kbytes of program memory is
mask programmable. A ROM protect feature prevents
“dumping” of the ROM contents by inhibiting execution of
LDC, LDCI, LDE, and LDEI instructions by external pro-
gram memory when pointing to internal memory locations.
Therefore these instructions can be used only when they
are executed from internal memory, or if they are executed
from external memory and pointing to external memory lo-
cations.
The ROM Protect option is mask-programmable, to be se-
lected by the customer at the time when the ROM code is
submitted.
Set working group 0 and Bank F
Load value into Port 4 using
working register addressing.
Load value into Port 4 using
absolute addressing.
Load value into Port 6 mode.
Set working group 1 and Bank F
Load value into general purpose
register 12H
Load value into general purpose
register 12H
Load value into Port 4
DS97Z8X1600
Zilog

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