Z86E7216VSC00TR Zilog, Z86E7216VSC00TR Datasheet - Page 76

• Manufacturer Part Number: Z86E7216VSC00TR
• Description: IC MCU OTP 16K ZIRC 44PLCC
• Manufacturer: Zilog
• Series: Z8®r

Specifications of Z86E7216VSC00TR

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 16MHz
• Peripherals: LVD, POR, WDT
• Number Of I /o: 31
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: OTP
• Ram Size: 748 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-LCC (J-Lead)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -

PS008704-0507
Watch-Dog Timer Mode Register (WDTMR)
The WDT is a retriggerable one-shot timer that resets the Z8 if it reaches its termi-
nal count. The WDT must initially be enabled by executing the WDT instruction
and refreshed on subsequent executions of the WDT instruction. The WDT circuit
is driven by an on-board RC oscillator or external oscillator from the XTAL1 pin.
The WDT instruction affects the Zero (Z), Sign (S), and Overflow (V) flags.
The POR clock source is selected with bit 4 of the WDT register. Bit 0 and 1 con-
trol a tap circuit that determines the time-out period. Bit 2 determines whether the
WDT is active during HALT, and Bit 3 determines WDT activity during STOP. Bits
5 through 7 are reserved. See
This register is accessible only during the first 60 processor cycles (SCLK) from
the execution of the first instruction after Power-On-Reset, Watch-Dog Reset, or a
Stop-Mode Recovery
be modified by any means, intentional or otherwise. The WDTMR cannot be read
and is located in Bank F of the Expanded Register Group at address location 0FH.
It is organized as shown in
* Default setting after reset
WDTMR (0F) FH
D7 D6 D5 D4 D3 D2 D1 D0
Figure 43. Watch-Dog Timer Mode Register—Write Only
(Figure 40
Figure
Figure
on page 68). After this point, the register cannot
43.
WDT TAP INT RC OSC
00
01*
10
11
WDT during HALT
0 = OFF
1 = ON*
43.
WDT during STOP
0 = OFF
1 = ON*
XTAL/INT RC Select for WDT
0 = On-Board RC*
1 = XTAL
Reserved (must be 0)
10 ms min
80 ms min
5 ms min
20 ms min
256 TpC
1024 TpC
External Clock
OTP Microcontroller
512 TpC
4096 TpC
72