MC9S08QG8MFQE Freescale Semiconductor, MC9S08QG8MFQE Datasheet - Page 77

• Manufacturer Part Number: MC9S08QG8MFQE
• Description: IC MCU 8K FLASH 8-DFN
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08QG8MFQE

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 4
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 8-DFN
• Processor Series: S08QG
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 4
• Number Of Timers: 1
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMO9S08QG8E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 4 Channel
• For Use With: DEMO9S08QG8E - BOARD DEMO FOR MC9S08QG8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

1
5.8.9
This high page register contains status and control bits to configure the stop mode behavior of the MCU.
See
Freescale Semiconductor
This bit can be written only one time after reset. Additional writes are ignored.
Reset:
PPDACK
PPDC
PPDF
Field
PDC
PDF
Section 3.6, “Stop
4
3
2
1
0
W
R
System Power Management Status and Control 2 Register
(SPMSC2)
Figure 5-11. System Power Management Status and Control 2 Register (SPMSC2)
Power Down Flag — This read-only status bit indicates the MCU has recovered from stop1 mode.
0 MCU has not recovered from stop1 mode.
1 MCU recovered from stop1 mode.
Partial Power Down Flag — This read-only status bit indicates that the MCU has recovered from stop2 mode.
0 MCU has not recovered from stop2 mode.
1 MCU recovered from stop2 mode.
Partial Power Down Acknowledge — Writing a 1 to PPDACK clears the PPDF and the PDF bits.
Power Down Control — The PDC bit controls entry into the power down (stop2 and stop1) modes.
0 Power down modes are disabled.
1 Power down modes are enabled.
Partial Power Down Control — The PPDC bit controls which power down mode is selected.
0 Stop1 full power down mode enabled if PDC set.
1 Stop2 partial power down mode enabled if PDC set.
0
0
7
= Unimplemented or Reserved
Modes,” for more information on stop modes.
0
0
6
Table 5-13. SPMSC2 Register Field Descriptions
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5
0
0
5
PDF
0
4
Description
Chapter 5 Resets, Interrupts, and General System Control
PPDF
3
0
PPDACK
0
0
2
PDC
0
1
1
PPDC
0
0
1
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