C8051T604-GM Silicon Laboratories Inc, C8051T604-GM Datasheet - Page 59
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C8051T604-GM
Manufacturer Part Number
C8051T604-GM
Description
IC 8051 MCU 2K-EEPROM 11-QFN
Manufacturer
Silicon Laboratories Inc
Series
C8051T60xr
Datasheet
1.C8051T600EDB.pdf
(188 pages)
Specifications of C8051T604-GM
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
8
Program Memory Size
2KB (2K x 8)
Program Memory Type
OTP
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
11-QFN
Processor Series
C8051T6x
Core
8051
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
I2C, SMBus, UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
8
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051T600DK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
For Use With
336-1404 - KIT DEV FOR C8051T60X MCU'S
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
336-1658-5
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051T604-GM
Manufacturer:
Silicon Laboratories Inc
Quantity:
135
13. Comparator0
C8051T600/1/2/3/4/5/6 devices include an on-chip programmable voltage comparator, Comparator0,
shown in Figure 13.1.
The Comparator offers programmable response time and hysteresis, an analog input multiplexer, and two
outputs that are optionally available at the Port pins: a synchronous “latched” output (CP0), or an asyn-
chronous “raw” output (CP0A). The asynchronous CP0A signal is available even when the system clock is
not active. This allows the Comparator to operate and generate an output with the device in STOP mode.
When assigned to a Port pin, the Comparator output may be configured as open drain or push-pull (see
Section “22.4. Port I/O Initialization” on page 114). Comparator0 may also be used as a reset source (see
Section “19.5. Comparator0 Reset” on page 94).
The Comparator0 inputs are selected by the comparator input multiplexer, as detailed in Section
“13.1. Comparator Multiplexer” on page 63.
The Comparator output can be polled in software, used as an interrupt source, and/or routed to a Port pin.
When routed to a Port pin, the Comparator output is available asynchronous or synchronous to the system
clock; the asynchronous output is available even in STOP mode (with no system clock active). When dis-
abled, the Comparator output (if assigned to a Port I/O pin via the Crossbar) defaults to the logic low state,
and the power supply to the comparator is turned off. See Section “22.3. Priority Crossbar Decoder” on
page 111 for details on configuring Comparator outputs via the digital Crossbar. Comparator inputs can be
CP0HYP1
CP0HYP0
CP0HYN1
CP0HYN0
CP0OUT
CP0RIF
CP0EN
CP0FIF
CP0MD1
CP0MD0
Figure 13.1. Comparator0 Functional Block Diagram
Comparator
Input Mux
CP0 +
CP0 -
+
-
VDD
GND
Rev. 1.2
Decision
Reset
Tree
(SYNCHRONIZER)
D
SET
CLR
Q
Q
C8051T600/1/2/3/4/5/6
D
SET
CLR
Q
Q
Interrupt Flag
Rising-edge
CP0
Crossbar
Interrupt
Logic
Interrupt Flag
Falling-edge
CP0
CP0A
CP0
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