MC9S08SH8CWJ Freescale Semiconductor, MC9S08SH8CWJ Datasheet - Page 152

• Manufacturer Part Number: MC9S08SH8CWJ
• Description: MCU 8BIT 8K FLASH 20-SOIC
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08SH8CWJ

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 17
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-SOIC (7.5mm Width)
• Processor Series: S08SH
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 2
• Operating Supply Voltage: 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMO9S08SG32, DEMO9S08SG32AUTO, DEMO9S08SG8, DEMO9S08SG8AUTO, DEMO9S08SH32, DEMO9S08SH8
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• A/d Bit Size: 10 bit
• A/d Channels Available: 12
• Height: 2.4 mm
• Length: 12.95 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Width: 7.6 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Chapter 10 Internal Clock Source (S08ICSV2)
10.1.4
There are seven modes of operation for the ICS: FEI, FEE, FBI, FBILP, FBE, FBELP, and stop.
10.1.4.1
In FLL engaged internal mode, which is the default mode, the ICS supplies a clock derived from the FLL
which is controlled by the internal reference clock. The BDC clock is supplied from the FLL.
10.1.4.2
In FLL engaged external mode, the ICS supplies a clock derived from the FLL which is controlled by an
external reference clock. The BDC clock is supplied from the FLL.
10.1.4.3
In FLL bypassed internal mode, the FLL is enabled and controlled by the internal reference clock, but is
bypassed. The ICS supplies a clock derived from the internal reference clock. The BDC clock is supplied
from the FLL.
152
Modes of Operation
FLL Engaged Interna
FLL Engaged External
FLL Bypassed Interna
RANGE
HGO
IREFS
Figure 10-2. Internal Clock Source (ICS) Block Diagram
External Reference
Clock Source
n=0-7
RDIV
Optional
/ 2
Block
n
MC9S08SH8 MCU Series Data Sheet, Rev. 3
IREFSTEN
EREFSTEN
Reference
Internal
RDIV_CLK
TRIM
Clock
EREFS
l (FEI)
9
l (FBI)
(FEE)
Filter
DCO
LP
FLL
ERCLKEN
IRCLKEN
9
Internal Clock Source Block
CLKS
DCOOUT
n=0-3
BDIV
/ 2
/ 2
n
ICSERCLK
ICSIRCLK
ICSOUT
ICSLCLK
ICSFFCLK
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