MC9S08QG84CFFER Freescale Semiconductor, MC9S08QG84CFFER Datasheet - Page 258
![IC MCU 8BIT 8K FLASH 16-QFN](/photos/38/65/386548/qfn-16_sml.jpg)
MC9S08QG84CFFER
Manufacturer Part Number
MC9S08QG84CFFER
Description
IC MCU 8BIT 8K FLASH 16-QFN
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet
1.MC9S08QG8CDTER.pdf
(314 pages)
Specifications of MC9S08QG84CFFER
Core Processor
HCS08
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
12
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
16-QFN
Data Bus Width
8 bit
Maximum Clock Frequency
20 MHz
Data Ram Size
512 B
On-chip Adc
Yes
Number Of Programmable I/os
12
Number Of Timers
1
Mounting Style
SMD/SMT
Height
1 mm
Interface Type
I2C, SCI, SPI
Length
5 mm
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Supply Voltage (max)
3.6 V
Supply Voltage (min)
1.8 V
Width
5 mm
For Use With
DEMO9S08QG8E - BOARD DEMO FOR MC9S08QG8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
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- Download datasheet (6Mb)
Development Support
17.3.6
The BRKEN control bit in the DBGC register may be set to 1 to allow any of the trigger conditions
described in
CPU. TAG in DBGC controls whether the breakpoint request will be treated as a tag-type breakpoint or a
force-type breakpoint. A tag breakpoint causes the current opcode to be marked as it enters the instruction
queue. If a tagged opcode reaches the end of the pipe, the CPU executes a BGND instruction to go to active
background mode rather than executing the tagged opcode. A force-type breakpoint causes the CPU to
finish the current instruction and then go to active background mode.
If the background mode has not been enabled (ENBDM = 1) by a serial WRITE_CONTROL command
through the BKGD pin, the CPU will execute an SWI instruction instead of going to active background
mode.
17.4
This section contains the descriptions of the BDC and DBG registers and control bits.
Refer to the high-page register summary in the device overview chapter of this data sheet for the absolute
address assignments for all DBG registers. This section refers to registers and control bits only by their
names. A Freescale-provided equate or header file is used to translate these names into the appropriate
absolute addresses.
17.4.1
The BDC has two registers:
These registers are accessed with dedicated serial BDC commands and are not located in the memory
space of the target MCU (so they do not have addresses and cannot be accessed by user programs).
Some of the bits in the BDCSCR have write limitations; otherwise, these registers may be read or written
at any time. For example, the ENBDM control bit may not be written while the MCU is in active
background mode. (This prevents the ambiguous condition of the control bit forbidding active background
mode while the MCU is already in active background mode.) Also, the four status bits (BDMACT, WS,
WSF, and DVF) are read-only status indicators and can never be written by the WRITE_CONTROL serial
BDC command. The clock switch (CLKSW) control bit may be read or written at any time.
256
•
•
The BDC status and control register (BDCSCR) is an 8-bit register containing control and status
bits for the background debug controller.
The BDC breakpoint match register (BDCBKPT) holds a 16-bit breakpoint match address.
Register Definition
Hardware Breakpoints
BDC Registers and Control Bits
Section 17.3.5, “Trigger
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5
Modes,”
to be used to generate a hardware breakpoint request to the
Freescale Semiconductor
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