S9S08SG8E2MTJ Freescale Semiconductor, S9S08SG8E2MTJ Datasheet - Page 308
S9S08SG8E2MTJ
Manufacturer Part Number
S9S08SG8E2MTJ
Description
MCU 2K FLASH 20-TSSOP
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet
1.S9S08SG4E2CSC.pdf
(316 pages)
Specifications of S9S08SG8E2MTJ
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
20-TSSOP
Processor Series
S08SG
Core
HCS08
Data Bus Width
8 bit
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMO9S08SG32, DEMO9S08SG32AUTO, DEMO9S08SG8, DEMO9S08SG8AUTO
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
S9S08SG8E2MTJ
Manufacturer:
FREESCALE
Quantity:
20 000
Company:
Part Number:
S9S08SG8E2MTJR
Manufacturer:
MICROCHIP
Quantity:
31 000
Part Number:
S9S08SG8E2MTJR
Manufacturer:
FREESCALE
Quantity:
20 000
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Appendix A Electrical Characteristics
A.12.3
Table A-15
308
1
2
3
4
5
and
SPI
Num
Maximum baud rate must be limited to 5 MHz due to input filter characteristics.
Refer to
All timing is shown with respect to 20% V
pins. All timing assumes slew rate control disabled and high drive strength enabled for SPI output
pins.
Time to data active from high-impedance state.
Hold time to high-impedance state.
10
11
12
1
2
3
4
5
6
7
8
9
Figure A-14
1
Figure A-14
D
D
D
D
D
D
D
D
D
D
D
D
C
Cycle time
Enable lead time
Enable lag time
Clock (SPSCK) high time
Clock (SPSCK) low time
Data setup time (inputs)
Data hold time (inputs)
Access time, slave
Disable time, slave
Data setup time (outputs)
Data hold time (outputs)
Operating frequency
through
through
Table A-15. SPI Electrical Characteristic
MC9S08SG8 MCU Series Data Sheet, Rev. 6
Rating
Figure A-17
Master and Slave
Master and Slave
Figure
3
4
2
A-17.
Master
Master
Master
Master
Master
Master
Master
Master
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
DD
describe the timing requirements for the SPI system.
and 70% V
Symbol
t
t
t
t
t
t
t
t
SCKH
SCKL
t
t
SI(M)
HI(M)
t
t
SI(S)
HI(S)
Lead
Lead
t
t
t
t
t
SCK
SCK
Lag
Lag
f
f
SO
SO
HO
HO
t
dis
op
op
A
DD
, unless noted; 100 pF load on all SPI
1/2 t
1/2 t
f
Bus
SCK
SCK
–10
–10
Min
1/2
1/2
30
30
30
30
25
25
dc
—
—
—
/2048
2
4
0
– 25
– 25
f
2048
Bus
Max
1/2
1/2
—
—
—
—
—
—
—
—
—
40
40
—
—
—
—
5
5
/4
Freescale Semiconductor
t
t
t
t
MHz
Unit
SCK
SCK
SCK
SCK
t
t
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
cyc
cyc
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