MC9S08QG8CFFE Freescale Semiconductor, MC9S08QG8CFFE Datasheet - Page 125

• Manufacturer Part Number: MC9S08QG8CFFE
• Description: IC MCU 8K FLASH 10MHZ 16-QFN
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08QG8CFFE

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 12
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 16-QFN
• Processor Series: S08QG
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 12
• Number Of Timers: 1
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMO9S08QG8E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• For Use With: DEMO9S08QG8E - BOARD DEMO FOR MC9S08QG8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

9.3.2
The ADCSC2 register is used to control the compare function, conversion trigger and conversion active
of the ADC module.
Freescale Semiconductor
ADTRG
ADACT
Field
1
7
6
Bits 1 and 0 are reserved bits that must always be written to 0.
Reset:
W
R
Status and Control Register 2 (ADCSC2)
Conversion Active — ADACT indicates that a conversion is in progress. ADACT is set when a conversion is
initiated and cleared when a conversion is completed or aborted.
0 Conversion not in progress
1 Conversion in progress
Conversion Trigger Select — ADTRG is used to select the type of trigger to be used for initiating a conversion.
Two types of trigger are selectable: software trigger and hardware trigger. When software trigger is selected, a
conversion is initiated following a write to ADCSC1. When hardware trigger is selected, a conversion is initiated
following the assertion of the ADHWT input.
0 Software trigger selected
1 Hardware trigger selected
ADACT
7
0
ADCH
00111
01000
01001
01010
01011
01100
01101
01110
01111
= Unimplemented or Reserved
ADTRG
Figure 9-5. Status and Control Register 2 (ADCSC2)
0
6
Table 9-4. ADCSC2 Register Field Descriptions
Figure 9-4. Input Channel Select (continued)
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5
Input Select
ACFE
0
5
AD10
AD11
AD12
AD13
AD14
AD15
AD7
AD8
AD9
ACFGT
0
4
Description
0
0
3
Analog-to-Digital Converter (S08ADC10V1)
ADCH
10111
11000
11001
11010
11011
11100
11101
11110
11111
0
0
2
R
0
1
1
Module disabled
Input Select
Reserved
V
V
AD23
AD24
AD25
AD26
AD27
REFH
REFL
R
0
0
1
123