MC9S08SH32CTJ Freescale Semiconductor, MC9S08SH32CTJ Datasheet - Page 181
![MCU 8BIT 32K FLASH 20-TSSOP](/photos/37/62/376250/landingpagefreescale8bit_sml.jpg)
MC9S08SH32CTJ
Manufacturer Part Number
MC9S08SH32CTJ
Description
MCU 8BIT 32K FLASH 20-TSSOP
Manufacturer
Freescale Semiconductor
Series
HCS08r
Specifications of MC9S08SH32CTJ
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
17
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-TSSOP
Processor Series
S08SH
Core
HCS08
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
I2C, SCI, SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
17
Number Of Timers
2
Operating Supply Voltage
5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMO9S08SG32, DEMO9S08SG32AUTO, DEMO9S08SG8, DEMO9S08SG8AUTO, DEMO9S08SH32, DEMO9S08SH8
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 16 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC9S08SH32CTJ
Manufacturer:
FREESCALE
Quantity:
20 000
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NOTES:
1. If general call is enabled, a check must be done to determine whether the received address was a general call address (0x00). If the received address was a
2. When 10-bit addressing is used to address a slave, the slave sees an interrupt following the first byte of the extended address. User software must ensure that for
Freescale Semiconductor
general call address, then the general call must be handled by user software.
this interrupt, the contents of IICD are ignored and not treated as a valid data transfer
Dummy Read
Switch to
from IICD
Rx Mode
Y
Transmitted
(Master Rx)
Byte to IICD
Addr Cycle
Write Next
Last Byte
RXAK=0
End of
?
?
?
Y
N
N
Stop Signal
TX
Generate
(MST = 0)
Y
N
Tx/Rx
Set TXACK =1
?
Figure 11-12. Typical IIC Interrupt Routine
Y
MC9S08SH8 MCU Series Data Sheet, Rev. 3
Byte to Be Read
Byte to Be Read
Read Data
from IICD
and Store
2nd Last
RX
Last
?
?
N
N
Stop Signal
Generate
(MST = 0)
Y
Y
RTI
Master
Mode
Clear
IICIF
?
Write Data
(Read)
Set TX
to IICD
Mode
N
N
Y
Dummy Read
Clear ARBL
from IICD
IAAS=1
Set RX
Chapter 11 Inter-Integrated Circuit (S08IICV2)
SRW=1
Mode
Y
?
?
N
Address Transfer
(Write)
See Note 1
Tx Next
Byte
Y
Y
Y
Dummy Read
Arbitration
ACK from
from IICD
Receiver
Switch to
IAAS=1
Rx Mode
TX/RX
Lost
?
?
?
?
N
N
N
Data Transfer
TX
See Note 2
Read Data
from IICD
and Store
RX
181
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