MC9S08QG8MPBE Freescale Semiconductor, MC9S08QG8MPBE Datasheet - Page 245
![IC MCU 8K FLASH 16-PDIP](/photos/12/33/123397/mc9s08qg8mpbe_sml.jpg)
MC9S08QG8MPBE
Manufacturer Part Number
MC9S08QG8MPBE
Description
IC MCU 8K FLASH 16-PDIP
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet
1.MC9S08QG8CDTER.pdf
(314 pages)
Specifications of MC9S08QG8MPBE
Core Processor
HCS08
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
12
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
16-DIP (0.300", 7.62mm)
Processor Series
S08QG
Core
HCS08
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SCI/SPI
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
12
Number Of Timers
1
Maximum Operating Temperature
+ 125 C
Mounting Style
Through Hole
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMO9S08QG8E
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
For Use With
DEMO9S08QG8E - BOARD DEMO FOR MC9S08QG8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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Chapter 17
Development Support
17.1
Introduction
Development support systems in the HCS08 include the background debug controller (BDC) and the
on-chip debug module (DBG). The BDC provides a single-wire debug interface to the target MCU that
provides a convenient interface for programming the on-chip FLASH and other nonvolatile memories. The
BDC is also the primary debug interface for development and allows non-intrusive access to memory data
and traditional debug features such as CPU register modify, breakpoints, and single instruction trace
commands.
In the HCS08 Family, address and data bus signals are not available on external pins. Debug is done
through commands fed into the target MCU via the single-wire background debug interface. The debug
module provides a means to selectively trigger and capture bus information so an external development
system can reconstruct what happened inside the MCU on a cycle-by-cycle basis without having external
access to the address and data signals.
17.1.1
Module Configuration
The alternate BDC clock source is the ICSLCLK. This clock source is selected by clearing the CLKSW
bit in the BDCSCR register. For details on ICSLCLK, see
Section 10.4, “Functional
Description” of the
ICS chapter.
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5
Freescale Semiconductor
243
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