MC9S08SH32CWL Freescale Semiconductor, MC9S08SH32CWL Datasheet - Page 156
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MC9S08SH32CWL
Manufacturer Part Number
MC9S08SH32CWL
Description
MCU 8BIT 32K FLASH 28-SOIC
Manufacturer
Freescale Semiconductor
Series
HCS08r
Specifications of MC9S08SH32CWL
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (7.5mm Width)
Processor Series
S08SH
Core
HCS08
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
I2C, SCI, SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
23
Number Of Timers
2
Operating Supply Voltage
5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMO9S08SG32, DEMO9S08SG32AUTO, DEMO9S08SG8, DEMO9S08SG8AUTO, DEMO9S08SH32, DEMO9S08SH8
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 16 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC9S08SH32CWL
Manufacturer:
FREESCALE
Quantity:
20 000
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Chapter 10 Internal Clock Source (S08ICSV2)
10.3.3
10.3.4
156
IREFST
CLKST
Field
TRIM
Field
3-2
7:0
7:5
4
Reset:
Reset:
POR:
POR:
W
W
R
R
ICS Trim Register (ICSTRM)
ICS Status and Control (ICSSC)
ICS Trim Setting — The TRIM bits control the internal reference clock frequency by controlling the internal
reference clock period. The bits’ effect are binary weighted (i.e., bit 1 will adjust twice as much as bit 0).
Increasing the binary value in TRIM will increase the period, and decreasing the value will decrease the period.
An additional fine trim bit is available in ICSSC as the FTRIM bit.
Reserved, should be cleared.
Internal Reference Status — The IREFST bit indicates the current source for the reference clock. The IREFST
bit does not update immediately after a write to the IREFS bit due to internal synchronization between clock
domains.
0 Source of reference clock is external clock.
1 Source of reference clock is internal clock.
Clock Mode Status — The CLKST bits indicate the current clock mode. The CLKST bits don’t update
immediately after a write to the CLKS bits due to internal synchronization between clock domains.
00
01
10
11
Output of FLL is selected.
FLL Bypassed, Internal reference clock is selected.
FLL Bypassed, External reference clock is selected.
Reserved.
U
7
1
7
0
0
0
Table 10-5. ICS Status and Control Register Field Descriptions
Figure 10-6. ICS Status and Control Register (ICSSC)
Table 10-4. ICS Trim Register Field Descriptions
U
0
0
0
0
6
6
Figure 10-5. ICS Trim Register (ICSTRM)
MC9S08SH8 MCU Series Data Sheet, Rev. 3
U
0
0
0
0
5
5
IREFST
U
0
1
1
4
4
Description
Description
TRIM
U
0
0
0
3
3
CLKST
U
0
0
0
2
2
OSCINIT
Freescale Semiconductor
U
0
0
0
1
1
FTRIM
U
U
0
0
0
0
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