MC908QB8MDTE Freescale Semiconductor, MC908QB8MDTE Datasheet - Page 188

• Manufacturer Part Number: MC908QB8MDTE
• Description: IC MCU 8BIT 8K FLASH 16-TSSOP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908QB8MDTE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 13
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 16-TSSOP
• Processor Series: HC08QB
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: 3-Wire, ESCI, SPI, UART
• Number Of Programmable I/os: 13
• Number Of Timers: 4
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68CBL05AE, DEMO908QB8, DEMO908QC16
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 10 Channel
• Controller Family/series: HC08
• No. Of I/o's: 14
• Ram Memory Size: 256Byte
• Cpu Speed: 8MHz
• No. Of Timers: 1
• Digital Ic Case Style: TSSOP
• Rohs Compliant: Yes
• For Use With: DEMO908QB8 - BOARD DEMO FOR MC68HC908QB8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Timer Interface Module (TIM)
ELSxB and ELSxA — Edge/Level Select Bits
TOVx — Toggle-On-Overflow Bit
CHxMAX — Channel x Maximum Duty Cycle Bit
16.8.5 TIM Channel Registers
These read/write registers contain the captured counter value of the input capture function or the output
compare value of the output compare function. The state of the TIM channel registers after reset is
unknown.
In input capture mode (MSxB:MSxA = 0:0), reading the high byte of the TIM channel x registers (TCHxH)
inhibits input captures until the low byte (TCHxL) is read.
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When channel x is an input capture channel, these read/write bits control the active edge-sensing logic
on channel x.
When channel x is an output compare channel, ELSxB and ELSxA control the channel x output
behavior when an output compare occurs.
When ELSxB and ELSxA are both clear, channel x is not connected to an I/O port, and pin TCHx is
available as a general-purpose I/O pin.
When channel x is an output compare channel, this read/write bit controls the behavior of the channel
x output when the counter overflows. When channel x is an input capture channel, TOVx has no effect.
When the TOVx bit is at 1, setting the CHxMAX bit forces the duty cycle of buffered and unbuffered
PWM signals to 100%. As
or cleared. The output stays at the 100% duty cycle level until the cycle after CHxMAX is cleared.
1 = Channel x pin toggles on counter overflow.
0 = Channel x pin does not toggle on counter overflow.
After initially enabling a TIM channel register for input capture operation
and selecting the edge sensitivity, clear CHxF to ignore any erroneous
edge detection flags.
When TOVx is set, a counter overflow takes precedence over a channel x
output compare if both occur at the same time.
CHxMAX
TCHx
OVERFLOW
Figure 16-13
COMPARE
PERIOD
OUTPUT
Figure 16-13. CHxMAX Latency
MC68HC908QB8 Data Sheet, Rev. 3
OVERFLOW
Table 16-2
shows, the CHxMAX bit takes effect in the cycle after it is set
COMPARE
OUTPUT
NOTE
NOTE
OVERFLOW
shows how ELSxB and ELSxA work.
COMPARE
OUTPUT
OVERFLOW
COMPARE
OUTPUT
OVERFLOW
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