MC9S08JM8CGT Freescale Semiconductor, MC9S08JM8CGT Datasheet - Page 248
![MCU 8BIT 8K FLASH 48-QFN](/photos/37/62/376240/qfn-48_sml.jpg)
MC9S08JM8CGT
Manufacturer Part Number
MC9S08JM8CGT
Description
MCU 8BIT 8K FLASH 48-QFN
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet
1.DEMO9S08JM16.pdf
(386 pages)
Specifications of MC9S08JM8CGT
Core Processor
HCS08
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, LIN, SCI, SPI, USB
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
37
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
48-QFN Exposed Pad
Processor Series
S08JM
Core
HCS08
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
I2C, SPI
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
37
Number Of Timers
2
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMOJM, DEMOJMSKT, DEMOFLEXISJMSD, DEMO9S08JM16
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 8 Channel
Package
48QFN EP
Family Name
HCS08
Maximum Speed
48 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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Serial Peripheral Interface (S08SPI16V1)
15.3.3
This register is used to set the prescaler and bit rate divisor for an SPI master. This register may be read or
written at any time.
248
SPPR[2:0]
SPR[2:0]
Reset
Field
6:4
2:0
W
R
SPI Baud Rate Register (SPIxBR)
SPI Baud Rate Prescale Divisor — This 3-bit field selects one of eight divisors for the SPI baud rate prescaler
as shown in
drives the input of the SPI baud rate divider (see
for details.
SPI Baud Rate Divisor — This 3-bit field selects one of eight divisors for the SPI baud rate divider as shown in
Table
Section 15.4.6, “SPI Baud Rate
0
0
7
Bidirectional
Bidirectional
Pin Mode
Normal
Normal
15-7. The input to this divider comes from the SPI baud rate prescaler (see
= Unimplemented or Reserved
Table
SPPR2
0
6
15-6. The input to this prescaler is the bus rate clock (BUSCLK). The output of this prescaler
Table 15-5. SPIxBR Register Field Descriptions
SPC0
Figure 15-7. SPI Baud Rate Register (SPIxBR)
Table 15-4. Bidirectional Pin Configurations
0
1
0
1
MC9S08JM16 Series Data Sheet, Rev. 2
SPPR1
0
5
BIDIROE
Generation,” for details.
Master Mode of Operation
Slave Mode of Operation
X
X
0
1
0
1
SPPR0
MISO not used by SPI
0
4
Figure
Description
Slave Out
Master In
Slave I/O
Slave In
MISO
15-15). See
3
0
0
Section 15.4.6, “SPI Baud Rate
MOSI not used by SPI
SPR2
0
2
Master Out
Master I/O
Master In
Slave In
MOSI
Figure
Freescale Semiconductor
SPR1
15-15). See
0
1
Generation,”
SPR0
0
0
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