MC908JK3EMDWER Freescale Semiconductor, MC908JK3EMDWER Datasheet - Page 168

• Manufacturer Part Number: MC908JK3EMDWER
• Description: MCU 8BIT 128RAM 4K FLASH 20-SOIC
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908JK3EMDWER

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Peripherals: LED, LVD, POR, PWM
• Number Of I /o: 15
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 20-SOIC (7.5mm Width)
• Processor Series: HC08JK
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 2
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908JL16E, M68CBL05CE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details

B.4 Reserved Registers
The two registers at $FE08 and $FE09 are reserved locations on the MC68H(R)C08JL3E/JK3E.
On the MC68H(R)C908JL3E/JK3E, these two locations are the Flash control register and the Flash block
protect register respectively.
B.5 Mask Option Registers
This section describes the mask option registers (MOR1 and MOR2). The mask option registers enable
or disable the following options:
B.5.1 Functional Description
The mask options are hard-wired connections, specified at the same time as the ROM code, which allow
the user to customize the MCU.
B.5.2 Mask Option Register 1 (MOR1)
COPRS — COP reset period selection bit
LVID — Low Voltage Inhibit Disable Bit
168
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1 = COP reset cycle is 8176 × 2OSCOUT
0 = COP reset cycle is 262,128 × 2OSCOUT
1 = Low Voltage Inhibit disabled
0 = Low Voltage Inhibit enabled
Stop mode recovery time (32 × 2OSCOUT cycles or 4096 × 2OSCOUT cycles)
STOP instruction
Computer operating properly module (COP)
COP reset period (COPRS), 8176 × 2OSCOUT or 262,128 × 2OSCOUT
Enable LVI circuit
Select LVI trip voltage
Address:
Reset:
Read:
Write:
COPRS
$001F
Bit 7
0
Figure 18-1. Mask Option Register 1 (MOR1)
= Unimplemented
MC68HC908JL3E Family Data Sheet, Rev. 4
6
0
0
5
0
0
LVID
4
0
3
0
0
SSREC
2
0
STOP
1
0
Freescale Semiconductor
COPD
Bit 0
0