MC9S08AC48MFDE Freescale Semiconductor, MC9S08AC48MFDE Datasheet - Page 177
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MC9S08AC48MFDE
Manufacturer Part Number
MC9S08AC48MFDE
Description
MCU 8BIT 48K FLASH 48-QFN
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet
1.MC9S08AC60CFJE.pdf
(348 pages)
Specifications of MC9S08AC48MFDE
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
38
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-QFN Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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10.5.7.1 FLL Engaged External Unlocked
FEE unlocked is entered when FEE is entered and the count error (Δn) output from the subtractor is greater
than the maximum n
unlock condition.
The ICG will remain in this state while the count error (Δn) is greater than the maximum n
the minimum n
In this state, the pulse counter, subtractor, digital loop filter, and DCO form a closed loop and attempt to
lock it according to their operational descriptions later in this section. Upon entering this state and until
the FLL becomes locked, the output clock signal ICGOUT frequency is given by f
extra divide by two prevents frequency overshoots during the initial locking process from exceeding
chip-level maximum frequency specifications. After the FLL has locked, if an unexpected loss of lock
causes it to re-enter the unlocked state while the ICG remains in FEE mode, the output clock signal
ICGOUT frequency is given by f
10.5.7.2 FLL Engaged External Locked
FEE locked is entered from FEE unlocked when the count error (Δn) is less than n
than n
condition. The output clock signal ICGOUT frequency is given by f
locked, the filter value is updated only once every four comparison cycles. The update made is an average
of the error measurements taken in the four previous comparisons.
10.5.8
To determine the FLL locked and loss-of-lock conditions, the pulse counter counts the pulses of the DCO
for one comparison cycle (see
to the subtractor. The subtractor compares this value to the value in MFD and produces a count error, Δn.
To achieve locked status, Δn must be between n
must stay between n
unexpectedly, the LOLS status bit is set and remains set until cleared by software or until the MCU is reset.
LOLS is cleared by reading ICGS1 then writing 1 to ICGIF (LOLRE = 0), or by a loss-of-lock induced
reset (LOLRE = 1), or by any MCU reset.
If the ICG enters the off state due to stop mode when ENBDM = OSCSTEN = 0, the FLL loses locked
status (LOCK is cleared), but LOLS remains unchanged because this is not an unexpected loss-of-lock
condition. Though it would be unusual, if ENBDM is cleared to 0 while the MCU is in stop, the ICG enters
the off state. Because this is an unexpected stopping of clocks, LOLS will be set when the MCU wakes up
from stop.
Expected loss of lock occurs when the MFD or CLKS bits are changed or in FEI mode only, when the
TRIM bits are changed. In these cases, the LOCK bit will be cleared until the FLL regains lock, but the
LOLS will not be set.
Freescale Semiconductor
lock
(min) for a given number of samples, as required by the lock detector to detect the lock
FLL Lock and Loss-of-Lock Detection
lock
, as required by the lock detector to detect the lock condition.
unlock
unlock
(min) and n
or less than the minimum n
Table 10-9
ICGDCLK
MC9S08AC60 Series Data Sheet, Rev. 2
unlock
for explanation of a comparison cycle) and passes this number
/ R.
(max) to remain locked. If Δn goes outside this range
lock
(min) and n
unlock
, as required by the lock detector to detect the
lock
Chapter 10 Internal Clock Generator (S08ICGV4)
ICGDCLK
(max). After the FLL has locked, Δn
/R. In FLL engaged external
ICGDCLK
lock
(max) and greater
lock
/ (2×R) This
or less than
177
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