S9S08AW32E5MFDE Freescale Semiconductor, S9S08AW32E5MFDE Datasheet - Page 37

• Manufacturer Part Number: S9S08AW32E5MFDE
• Description: MCU 32K FLASH AUTO MONET 48-QFN
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of S9S08AW32E5MFDE

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 38
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-QFN Exposed Pad
• Processor Series: S08AW
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 2
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMO9S08AW60E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

3.6.4
The LVD system is capable of generating either an interrupt or a reset when the supply voltage drops below
the LVD voltage. If the LVD is enabled in stop by setting the LVDE and the LVDSE bits, then the voltage
regulator remains active during stop mode. If the user attempts to enter stop2 with the LVD enabled for
stop, the MCU will instead enter stop3.
LVD is enabled.
3.6.5
When the MCU enters any stop mode, system clocks to the internal peripheral modules are stopped. Even
in the exception case (ENBDM = 1), where clocks to the background debug logic continue to operate,
clocks to the peripheral systems are halted to reduce power consumption. Refer to
Mode,” and
Freescale Semiconductor
1
Mode
Stop3
Mode
Stop3
Crystal oscillator can be configured to run in stop3. Please see the ICG registers.
LVD Enabled in Stop Mode
On-Chip Peripheral Modules in Stop Modes
Section 3.6.2, “Stop3
PPDC
PPDC
0
0
CPU
RAM
FLASH
Parallel Port Registers
ADC1
ICG
IIC
CPU, Digital
Peripherals,
CPU, Digital
Peripherals,
Standby
Standby
FLASH
FLASH
Peripheral
Table 3-2. BDM Enabled Stop Mode Behavior
Table 3-3. LVD Enabled Stop Mode Behavior
Mode,” for specific information on system behavior in stop modes.
Standby
Standby
RAM
RAM
Table 3-4. Stop Mode Behavior
MC9S08AW60 Data Sheet, Rev 2
Table 3-3
Active
ICG
ICG
Off
1
summarizes the behavior of the MCU in stop when the
Standby
Optionally on
Optionally on
Stop2
Off
Off
Off
Off
Off
Off
ADC1
ADC1
Mode
Regulator
Regulator
Active
Active
Optionally On
Optionally On
Standby
Standby
Standby
Standby
Standby
Stop3
I/O Pins
I/O Pins
States
States
held
held
1
2
Chapter 3 Modes of Operation
Section 3.6.1, “Stop2
Optionally on
Optionally on
RTI
RTI
37