MC9S12P96CFT Freescale Semiconductor, MC9S12P96CFT Datasheet - Page 288
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MC9S12P96CFT
Manufacturer Part Number
MC9S12P96CFT
Description
MCU 16BIT 96K FLASH 48-QFN
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.S9S12P32J0MFT.pdf
(566 pages)
Specifications of MC9S12P96CFT
Core Processor
HCS12
Core Size
16-Bit
Speed
32MHz
Connectivity
CAN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
96KB (96K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 10x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-QFN Exposed Pad
Processor Series
S12P
Core
HCS12
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
KIT33812ECUEVME, DEMO9S12PFAME
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Freescale’s Scalable Controller Area Network (S12MSCANV3)
The MSCAN then schedules the message for transmission and signals the successful transmission of the
buffer by setting the associated TXE flag. A transmit interrupt (see
is generated
If more than one buffer is scheduled for transmission when the CAN bus becomes available for arbitration,
the MSCAN uses the local priority setting of the three buffers to determine the prioritization. For this
purpose, every transmit buffer has an 8-bit local priority field (PRIO). The application software programs
this field when the message is set up. The local priority reflects the priority of this particular message
relative to the set of messages being transmitted from this node. The lowest binary value of the PRIO field
is defined to be the highest priority. The internal scheduling process takes place whenever the MSCAN
arbitrates for the CAN bus. This is also the case after the occurrence of a transmission error.
When a high priority message is scheduled by the application software, it may become necessary to abort
a lower priority message in one of the three transmit buffers. Because messages that are already in
transmission cannot be aborted, the user must request the abort by setting the corresponding abort request
bit (ABTRQ) (see
(CANTARQ)”.) The MSCAN then grants the request, if possible, by:
8.4.2.3
The received messages are stored in a five stage input FIFO. The five message buffers are alternately
mapped into a single memory area (see
associated with the MSCAN, but the foreground receive buffer (RxFG) is addressable by the CPU (see
Figure
the receive process.
All receive buffers have a size of 15 bytes to store the CAN control bits, the identifier (standard or
extended), the data contents, and a time stamp, if enabled (see
Message
The receiver full flag (RXF) (see
the status of the foreground receive buffer. When the buffer contains a correctly received message with a
matching identifier, this flag is set.
On reception, each message is checked to see whether it passes the filter (see
Acceptance
valid message, the MSCAN shifts the content of RxBG into the receiver FIFO
generates a receive interrupt (see
handler must read the received message from the RxFG and then reset the RXF flag to acknowledge the
interrupt and to release the foreground buffer. A new message, which can follow immediately after the IFS
field of the CAN frame, is received into the next available RxBG. If the MSCAN receives an invalid
1. The transmit interrupt occurs only if not masked. A polling scheme can be applied on TXEx also.
2. Only if the RXF flag is not set.
3. The receive interrupt occurs only if not masked. A polling scheme can be applied on RXF also.
288
1. Setting the corresponding abort acknowledge flag (ABTAK) in the CANTAAK register.
2. Setting the associated TXE flag to release the buffer.
3. Generating a transmit interrupt. The transmit interrupt handler software can determine from the
8-39). This scheme simplifies the handler software because only one address area is applicable for
setting of the ABTAK flag whether the message was aborted (ABTAK = 1) or sent (ABTAK = 0).
Storage”).
1
Filter”) and simultaneously is written into the active RxBG. After successful reception of a
Receive Structures
when TXEx is set and can be used to drive the application software to re-load the buffer.
Section 8.3.2.9, “MSCAN Transmitter Message Abort Request Register
Section 8.3.2.5, “MSCAN Receiver Flag Register
Section 8.4.7.3, “Receive
S12P-Family Reference Manual, Rev. 1.13
Figure
8-39). The background receive buffer (RxBG) is exclusively
Interrupt”) to the CPU
Section 8.3.3, “Programmer’s Model of
Section 8.4.7.2, “Transmit
Section 8.4.3, “Identifier
2
, sets the RXF flag, and
(CANRFLG)”) signals
3
. The user’s receive
Freescale Semiconductor
Interrupt”)
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