MC9S08DZ16AMLC Freescale Semiconductor, MC9S08DZ16AMLC Datasheet - Page 217
MC9S08DZ16AMLC
Manufacturer Part Number
MC9S08DZ16AMLC
Description
IC MCU 16K FLASH 1K RAM 32-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS08r
Specifications of MC9S08DZ16AMLC
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, I²C, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
25
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 10x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
32-LQFP
Processor Series
S08DZ
Core
HCS08
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
CAN, I2C, SCI, SPI
Number Of Programmable I/os
26
Number Of Timers
2
Operating Supply Voltage
5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMO9S08DZ60
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 10 Channel
Controller Family/series
HCS08
No. Of I/o's
25
Eeprom Memory Size
512Byte
Ram Memory Size
1KB
Cpu Speed
40MHz
No. Of Timers
2
Digital Ic Case Style
LQFP
Rohs Compliant
Yes
For Use With
EVB9S08DZ60 - BOARD EVAL FOR 9S08DZ60
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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NOTES:
1. If general call is enabled, a check must be done to determine whether the received address was a general call address (0x00). If the received address was a
2. When 10-bit addressing is used to address a slave, the slave sees an interrupt following the first byte of the extended address. User software must ensure that for
Freescale Semiconductor
general call address, then the general call must be handled by user software.
this interrupt, the contents of IICD are ignored and not treated as a valid data transfer
Dummy Read
Switch to
from IICD
Rx Mode
Y
Transmitted
(Master Rx)
Byte to IICD
Addr Cycle
Write Next
Last Byte
RXAK=0
End of
?
?
?
Y
N
N
Stop Signal
TX
Generate
(MST = 0)
Y
N
Tx/Rx
Set TXACK =1
?
Figure 11-12. Typical IIC Interrupt Routine
Y
Byte to Be Read
Byte to Be Read
MC9S08DZ60 Series Data Sheet, Rev. 4
Read Data
from IICD
and Store
2nd Last
RX
Last
?
?
N
N
Stop Signal
Generate
(MST = 0)
Y
Y
RTI
Master
Mode
Clear
IICIF
?
Write Data
(Read)
Set TX
to IICD
Mode
N
N
Y
Dummy Read
Clear ARBL
from IICD
IAAS=1
Set RX
Chapter 11 Inter-Integrated Circuit (S08IICV2)
SRW=1
Mode
Y
?
?
N
Address Transfer
(Write)
See Note 1
Tx Next
Byte
Y
Y
Y
Dummy Read
Arbitration
ACK from
from IICD
Receiver
Switch to
IAAS=1
Rx Mode
TX/RX
Lost
?
?
?
?
N
N
N
Data Transfer
TX
See Note 2
Read Data
from IICD
and Store
RX
217
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