MC9S12P96VFT Freescale Semiconductor, MC9S12P96VFT Datasheet - Page 97
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MC9S12P96VFT
Manufacturer Part Number
MC9S12P96VFT
Description
MCU 16BIT 96K FLASH 48-QFN
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.S9S12P32J0MFT.pdf
(566 pages)
Specifications of MC9S12P96VFT
Core Processor
HCS12
Core Size
16-Bit
Speed
32MHz
Connectivity
CAN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
96KB (96K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 10x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
48-QFN Exposed Pad
Processor Series
S12P
Core
HCS12
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
KIT33812ECUEVME, DEMO9S12PFAME
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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1. Read: Anytime. The data source is depending on the data direction value.
1. Read: Anytime
2.3.58
2.3.59
Freescale Semiconductor
Function
Address 0x0271
Address 0x0272
DDR0AD
Write: Anytime
PT1AD
Write: Anytime
Altern.
Field
Field
Reset
Reset
7-0
1-0
W
W
R
R
Port AD general purpose input/output data—Data Register, ATD AN analog input
When not used with the alternative function, the associated pin can be used as general purpose I/O. In general
purpose output mode the register bit value is driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port register bit, otherwise the buffered
pin input state is read.
Port AD data direction—
This bit determines whether the associated pin is an input or output.
To use the digital input function the ATD Digital Input Enable Register (ATDDIEN) has to be set to logic level “1”.
1 Associated pin is configured as output
0 Associated pin is configured as input
PT1AD7
Port AD Data Register (PT1AD)
Port AD Data Direction Register (DDR0AD)
AN7
0
0
0
7
7
PT1AD6
AN6
Figure 2-57. Port AD Data Direction Register (DDR0AD)
0
0
0
6
6
Table 2-53. DDR0AD Register Field Descriptions
Table 2-52. PT1AD Register Field Descriptions
Figure 2-56. Port AD Data Register (PT1AD)
S12P-Family Reference Manual, Rev. 1.13
PT1AD5
AN5
5
0
5
0
0
PT1AD4
AN4
0
0
0
4
4
Description
Description
PT1AD3
AN3
0
0
0
3
3
PT1AD2
AN2
0
0
0
2
2
Port Integration Module (S12PPIMV1)
DDR0AD1
Access: User read/write
Access: User read/write
PT1AD1
AN1
0
0
1
1
DDR0AD0
PT1AD0
AN0
0
0
0
0
97
(1)
(1)
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