S9S08AW60E5MFDE Freescale Semiconductor, S9S08AW60E5MFDE Datasheet - Page 161
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S9S08AW60E5MFDE
Manufacturer Part Number
S9S08AW60E5MFDE
Description
MCU 64K FLASH AUTO MONET 48-QFN
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet
1.MC9S08AW32CFDE.pdf
(324 pages)
Specifications of S9S08AW60E5MFDE
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
38
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-QFN Exposed Pad
Controller Family/series
HCS08
No. Of I/o's
38
Ram Memory Size
2KB
Cpu Speed
40MHz
No. Of Timers
2
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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9.4.1
Freescale Semiconductor
KBEDG[7:4]
KBIMOD
Reset
KBACK
Field
KBIE
KBF
7:4
3
2
1
W
R
KBEDG7
KBI Status and Control Register (KBI1SC)
Keyboard Edge Select for KBI Port Bits — Each of these read/write bits selects the polarity of the edges and/or
levels that are recognized as trigger events on the corresponding KBI port pin when it is configured as a keyboard
interrupt input (KBIPEn = 1). Also see the KBIMOD control bit, which determines whether the pin is sensitive to
edges-only or edges and levels.
0 Falling edges/low levels
1 Rising edges/high levels
Keyboard Interrupt Flag — This read-only status flag is set whenever the selected edge event has been
detected on any of the enabled KBI port pins. This flag is cleared by writing a 1 to the KBACK control bit. The
flag will remain set if KBIMOD = 1 to select edge-and-level operation and any enabled KBI port pin remains at
the asserted level.
KBF can be used as a software pollable flag (KBIE = 0) or it can generate a hardware interrupt request to the
CPU (KBIE = 1).
0 No KBI interrupt pending
1 KBI interrupt pending
Keyboard Interrupt Acknowledge — This write-only bit (reads always return 0) is used to clear the KBF status
flag by writing a 1 to KBACK. When KBIMOD = 1 to select edge-and-level operation and any enabled KBI port
pin remains at the asserted level, KBF is being continuously set so writing 1 to KBACK does not clear the KBF
flag.
Keyboard Interrupt Enable — This read/write control bit determines whether hardware interrupts are generated
when the KBF status flag equals 1. When KBIE = 0, no hardware interrupts are generated, but KBF can still be
used for software polling.
0 KBF does not generate hardware interrupts (use polling)
1 KBI hardware interrupt requested when KBF = 1
Keyboard Detection Mode — This read/write control bit selects either edge-only detection or edge-and-level
detection. KBI port bits 3 through 0 can detect falling edges-only or falling edges and low levels. KBI port bits 7
through 4 can be configured to detect either:
0 Edge-only detection
1 Edge-and-level detection
0
7
• Rising edges-only or rising edges and high levels (KBEDGn = 1)
• Falling edges-only or falling edges and low levels (KBEDGn = 0)
= Unimplemented or Reserved
KBEDG6
0
6
Figure 9-3. KBI Status and Control Register (KBI1SC)
Table 9-2. KBI1SC Register Field Descriptions
KBEDG5
0
5
MC9S08AW60 Data Sheet, Rev 2
KBEDG4
0
4
Description
KBF
3
0
KBACK
Chapter 9 Keyboard Interrupt (S08KBIV1)
0
0
2
KBIE
0
1
KBIMOD
0
0
161
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