C8051F338-GMR Silicon Laboratories Inc, C8051F338-GMR Datasheet
C8051F338-GMR
Manufacturer Part Number
C8051F338-GMR
Description
IC MCU 16K FLASH 24QFN
Manufacturer
Silicon Laboratories Inc
Series
C8051F33xr
Specifications of C8051F338-GMR
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
21
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
24-QFN
Processor Series
C8051F3x
Core
8051
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
21
Number Of Timers
4
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
KSK-SL-TOOLSTICK, PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F336DK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
On-chip Dac
10 bit
Height
0.73 mm
Length
4 mm
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2.7 V
Width
4 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
Q4962654
T1084322
T1084322
Analog Peripherals
10-Bit ADC
-
-
-
-
-
10-bit DAC (Current Mode)
Comparator
-
-
-
On-Chip Debug
-
-
-
-
Supply Voltage: 2.7 to 3.6 V
Temperature Range: –40 to +85 °C
Small Form Factor
Programmable throughput up to 200 ksps
Up to 16 external inputs; programmable as single-ended or differential
Reference from internal V
Internal or external start of conversion sources
Built-in temperature sensor
Programmable hysteresis and response time
Configurable to generate interrupts or reset
Low current
On-chip debug circuitry facilitates full speed, non-intrusive in-system
debug (no emulator required)
Provides breakpoints, single stepping, watchpoints
Inspect/modify memory, registers, and stack
Superior performance to emulation systems using ICE-chips, target
pods, and sockets
C2CK/RST
GND
VDD
Power Net
Programming
C2D
Power On
Hardware
Debug /
Reset
XTAL1
XTAL2
REF
, V
Reset
DD
, or external pin
25 MIPS, 16 kB Flash, 10-Bit ADC, 24-pin Mixed-Signal MCU
Low-Freq.
24.5 MHz
Oscillator
Oscillator
Oscillator
Precision
Controller Core
External
Program Memory
System Clock
Circuit
Configuration
CIP-51 8051
16 kB ISP Flash
256 Byte SRAM
512 Byte XRAM
Copyright © 2007 by Silicon Laboratories
SYSCLK
SFR
Bus
High-Speed 8051 µC Core
-
-
-
Memory
-
-
Digital Peripherals
-
-
-
-
-
-
-
-
-
-
Package
-
C8051F338 Only
VDD
Timers 0,
SMBus
10-bit
IDAC
10-bit
200 ksps
ADC
Pipelined instruction architecture; executes 70% of instructions in 1 or 2
system clocks
Up to 25 MIPS throughput with 25 MHz clock
Expanded interrupt handler
768 bytes data RAM
16 kB Flash; in-system programmable in 512 byte sectors
21 port I/O; all are 5 V tolerant
Hardware SMBus™ (I
serial ports available concurrently
Programmable 16-bit counter/timer array with three capture/compare
modules, WDT
4 general-purpose 16-bit counter/timers
Timer with real-time clock mode
Clock sources
Two internal oscillators:
External oscillator: Crystal, RC, C, or Clock (1 or 2 pin modes)
Can switch between clock sources on-the-fly
Suspend mode for maximum power savings with fast wake-up (<1 us)
24-pin QFN
UART
1, 2, 3
Analog Peripherals
Digital Peripherals
PCA/
(512 bytes are reserved)
WDT
Port I/O Configuration
SPI
CP0, CP0A
-
-
Crossbar Control
Precision 24.5 MHz, 2% accuracy over V
80 kHz low frequency, low-power
VREF
Comparator
M
A
U
X
+
Crossbar
-
Decoder
Priority
IDA0
Sensor
VREF
Temp
GND
VDD
2
C™ compatible), SPI™, and crystaless-UART
Drivers
Drivers
Drivers
Port 0
Port 1
Port 2
C8051F338
DD
and temperature
P0.0/VREF
P0.1/IDA0
P0.2/XTAL1
P0.3/XTAL2
P0.4/TX
P0.5/RX
P0.6/CNVSTR
P0.7
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P2.0
P2.1
P2.2
P2.3
P2.4/C2D
08.13.2007
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C8051F338-GMR Summary of contents
Page 1
... Crossbar Control SFR Bus Analog Peripherals 10-bit IDAC VDD VREF A 10-bit M 200 ksps U ADC X C8051F338 Only CP0, CP0A Comparator Copyright © 2007 by Silicon Laboratories C8051F338 2 C™ compatible), SPI™, and crystaless-UART and temperature DD P0.0/VREF P0.1/IDA0 P0.2/XTAL1 P0.3/XTAL2 Port 0 Drivers P0.4/TX P0 ...
Page 2
... Clock = 32 kHz; V monitor disabled DD Oscillator off; V monitor disabled DD Guaranteed monotonic Guaranteed monotonic (CP+) – (CP–) = 100 mV (CP+) – (CP–) = 100 mV (CP+) – (CP–) = 100 mV (CP+) – (CP–) = 100 mV C8051F338DK Development Kit Millimeters Min Nom Max 2.00 2.10 2.20 0.30 0.40 0.50 0.03 ...