C8051F353-GMR Silicon Laboratories Inc, C8051F353-GMR Datasheet - Page 123
![IC 8051 MCU 8K FLASH 28MLP](/photos/6/93/69391/sl-28-mlp_sml.jpg)
C8051F353-GMR
Manufacturer Part Number
C8051F353-GMR
Description
IC 8051 MCU 8K FLASH 28MLP
Manufacturer
Silicon Laboratories Inc
Series
C8051F35xr
Specifications of C8051F353-GMR
Core Processor
8051
Core Size
8-Bit
Speed
50MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
17
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x16b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Processor Series
C8051F3x
Core
8051
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
I2C, SMBus, SPI, UART
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
17
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
KSK-SL-TOOLSTICK, PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F350DK
Minimum Operating Temperature
- 40 C
On-chip Adc
16 bit, 8 Channel
On-chip Dac
8 bit, 2 Channel
For Use With
336-1083 - DEV KIT FOR F350/351/352/353
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
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15.2. Non-volatile Data Storage
The Flash memory can be used for non-volatile data storage as well as program code. This allows data
such as calibration coefficients to be calculated and stored at run time. Data is written using the MOVX
write instruction and read using the MOVC instruction. Note: MOVX read instructions always target XRAM.
15.3. Security Options
The CIP-51 provides security options to protect the Flash memory from inadvertent modification by soft-
ware as well as to prevent the viewing of proprietary program code and constants. The Program Store
Write Enable (bit PSWE in register PSCTL) and the Program Store Erase Enable (bit PSEE in register
PSCTL) bits protect the Flash memory from accidental modification by software. PSWE must be explicitly
set to ‘1’ before software can modify the Flash memory; both PSWE and PSEE must be set to ‘1’ before
software can erase Flash memory. Additional security features prevent proprietary program code and data
constants from being read or altered across the C2 interface.
A Security Lock Byte located at the last byte of Flash user space offers protection of the Flash program
memory from access (reads, writes, or erases) by unprotected code or the C2 interface. The Flash security
mechanism allows the user to lock n 512-byte Flash pages, starting at page 0 (addresses 0x0000 to
0x01FF), where n is the 1’s complement number represented by the Security Lock Byte. Note that the
page containing the Flash Security Lock Byte is locked when any other Flash pages are locked. See exam-
ple below.
Flash pages locked:
Security Lock Byte:
Addresses locked:
1’s Complement:
other Flash pages are
according to the Flash
Locked when any
security lock byte
Access limit set
locked
Figure 15.1. Flash Memory Map
Unlocked Flash Pages
0x0000 to 0x03FF (first two Flash pages) and
3 (First two Flash pages + Lock Byte Page)
Lock Byte
Reserved
0x1C00 to 0x1DFF (Lock Byte Page)
Rev. 1.1
00000010b
11111101b
0x1E00
0x1DFF
0x1DFE
0x1C00
0x0000
C8051F350/1/2/3
Flash memory organized
in 512-byte pages
123
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