MC9S08DV128CLF Freescale Semiconductor, MC9S08DV128CLF Datasheet - Page 134

• Manufacturer Part Number: MC9S08DV128CLF
• Description: MCU 8BIT 128K FLASH 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08DV128CLF

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Processor Series: S08DV
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 6 KB
• Interface Type: CAN, I2C, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 87
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMO9S08DZ60
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 24 Channel
• A/d Bit Size: 12 bit
• A/d Channels Available: 24
• Height: 1.4 mm
• Length: 7 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Width: 7 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Chapter 6 Parallel Input/Output Control
6.5.9.5
6.5.9.6
134
PTJDS[7:0]
Reset:
Reset:
PTJMOD
PTJACK
PTJIF
PTJIE
Field
Field
7:0
3
2
1
0
W
W
R
R
PTJDS7
Output Drive Strength Selection for Port J Bits — Each of these control bits selects between low and high
output drive for the associated PTJ pin. For port J pins that are configured as inputs, these bits have no effect.
0 Low output drive strength selected for port J bit n.
1 High output drive strength selected for port J bit n.
Port J Interrupt Flag — PTJIF indicates when a port J interrupt is detected. Writes have no effect on PTJIF.
0 No port J interrupt detected.
1 Port J interrupt detected.
Port J Interrupt Acknowledge — Writing a 1 to PTJACK is part of the flag clearing mechanism. PTJACK always
reads as 0.
Port J Interrupt Enable — PTJIE determines whether a port J interrupt is requested.
0 Port J interrupt request not enabled.
1 Port J interrupt request enabled.
Port J Detection Mode — PTJMOD (along with the PTJES bits) controls the detection mode of the port J
interrupt pins.
0 Port J pins detect edges only.
1 Port J pins detect both edges and levels.
Port J Drive Strength Selection Register (PTJDS)
0
Port J Interrupt Status and Control Register (PTJSC)
0
0
7
7
Figure 6-57. Port J Interrupt Status and Control Register (PTJSC)
Figure 6-56. Drive Strength Selection for Port J Register (PTJDS)
= Unimplemented or Reserved
PTJDS6
0
0
0
6
6
Table 6-54. PTJDS Register Field Descriptions
Table 6-55. PTJSC Register Field Descriptions
MC9S08DZ128 Series Data Sheet, Rev. 1
PTJDS5
0
0
0
5
5
PTJDS4
0
0
0
4
4
Description
Description
PTJDS3
PTJIF
3
0
3
0
PTJDS2
PTJACK
0
0
0
2
2
PTJDS1
Freescale Semiconductor
PTJIE
0
0
1
1
PTJMOD
PTJDS0
0
0
0
0