MC9S08AW32CFGE Freescale Semiconductor, MC9S08AW32CFGE Datasheet - Page 106
![IC MCU 32K FLASH 44-LQFP](/photos/12/35/123573/mc9s08aw16mfge_sml.jpg)
MC9S08AW32CFGE
Manufacturer Part Number
MC9S08AW32CFGE
Description
IC MCU 32K FLASH 44-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS08r
Specifications of MC9S08AW32CFGE
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-LQFP
Processor Series
S08AW
Core
HCS08
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
I2C, SCI, SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
34
Number Of Timers
8
Operating Supply Voltage
- 0.3 V to + 5.8 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMO9S08AW60E
Minimum Operating Temperature
- 55 C
On-chip Adc
10 bit, 8 Channel
Package
44LQFP
Family Name
HCS08
Maximum Speed
40 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
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Manufacturer
Quantity
Price
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Chapter 6 Parallel Input/Output
6.7.13
Port G parallel I/O function is controlled by the registers listed below.
106
PTGDD[6:0]
PTGD[6:0]
Reset
Reset
Field
Field
6:0
6:0
W
W
R
R
Port G I/O Registers (PTGD and PTGDD)
Port G Data Register Bits — For port G pins that are inputs, reads return the logic level on the pin. For port G
pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port G pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTGD to all 0s, but these 0s are not driven out the corresponding pins because reset also
configures all port pins as high-impedance inputs with pullups disabled.
Data Direction for Port G Bits — These read/write bits control the direction of port G pins and what is read for
PTGD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port G bit n and PTGD reads return the contents of PTGDn.
0
0
7
7
PTGDD6
PTGD6
0
0
6
6
Table 6-33. PTGDD Register Field Descriptions
Figure 6-40. Data Direction for Port G (PTGDD)
Table 6-32. PTGD Register Field Descriptions
Figure 6-39. Port G Data Register (PTGD)
PTGDD5
PTGD5
0
0
5
5
MC9S08AW60 Data Sheet, Rev 2
PTGDD4
PTGD4
0
0
4
4
Description
Description
PTGDD3
PTGD3
3
0
3
0
PTGDD2
PTGD2
0
0
2
2
PTGDD1
Freescale Semiconductor
PTGD1
0
0
1
1
PTGDD0
PTGD0
0
0
0
0
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