MC9S08DZ128CLF Freescale Semiconductor, MC9S08DZ128CLF Datasheet - Page 66

• Manufacturer Part Number: MC9S08DZ128CLF
• Description: MCU 8BIT 128K FLASH 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08DZ128CLF

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Package: 48LQFP
• Family Name: HCS08
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 87
• Interface Type: CAN/I2C/SPI/UART
• On-chip Adc: 24-chx12-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 4 Memory
4.5
The MC9S08DZ128 Series includes static RAM. The locations in RAM below 0x0100 can be accessed
using the more efficient direct addressing mode, and any single bit in this area can be accessed with the bit
manipulation instructions (BCLR, BSET, BRCLR, and BRSET). Locating the most frequently accessed
program variables in this area of RAM is preferred.
The RAM retains data while the MCU is in low-power wait, stop2, or stop3 mode. At power-on the
contents of RAM are uninitialized. RAM data is unaffected by any reset if the supply voltage does not drop
below the minimum value for RAM retention (V
For compatibility with M68HC05 MCUs, the HCS08 resets the stack pointer to 0x00FF. In the
MC9S08DZ128 Series, it is usually best to reinitialize the stack pointer to the top of the RAM so the direct
page RAM can be used for frequently accessed RAM variables and bit-addressable program variables.
Include the following 2-instruction sequence in your reset initialization routine (where RamLast is equated
to the highest address of the RAM in the Freescale Semiconductor equate file).
When security is enabled, the RAM is considered a secure memory resource and is not accessible through
BDM or code executing from non-secure memory. See
of the security feature.
66
D7:D0
Field
7:0
Reset:
RAM
W
R
The 2s complement value written to LAPAB will be added to contents of the linear address pointer register,
LAP2:LAP0. Writing a value of 0x7f to LAPAB will increase LAP by 127, a value of 0x80 will decrease LAP by
128, and a value of 0xff will decrease LAP by 1.
LDHX
TXS
On most devices in the MC9S08DZ128 Series, more than 4K of RAM is
present in two separate address blocks.
Table 4-11. Linear Address Pointer Add Byte Register Field Descriptions
D7
0
0
7
Figure 4-10. Linear Address Pointer Add Byte Register (LAPAB)
#RamLast+1
D6
0
0
6
MC9S08DZ128 Series Data Sheet, Rev. 1
D5
;point one past RAM
;SP<-(H:X-1)
5
0
0
RAM
NOTE
D4
0
0
4
).
Description
Section 4.6.9,
D3
0
0
3
“Security”, for a detailed description
D2
0
0
2
D1
0
0
1
Freescale Semiconductor
D0
0
0
0