MC908LJ12CFBE Freescale Semiconductor, MC908LJ12CFBE Datasheet - Page 355

• Manufacturer Part Number: MC908LJ12CFBE
• Description: IC MCU 12K FLASH 8MHZ 52-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908LJ12CFBE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: IRSCI, SPI
• Peripherals: LCD, LVD, POR, PWM
• Number Of I /o: 20
• Program Memory Size: 12KB (12K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-LQFP
• Processor Series: HC08LJ
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V, 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68EML08LJLKE, ZK-HC08LX-A, M68CBL05CE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 6-ch x 10-bit
• Controller Family/series: HC08
• No. Of I/o's: 20
• Ram Memory Size: 512Byte
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

17.6.2 Data Direction Register D (DDRD)
MC68HC908LJ12
Freescale Semiconductor
NOTE:
NOTE:
—
Rev. 2.1
Address:
KBI[7:4] — Keyboard Interrupt Pins
Data direction register D determines whether each port D pin is an input
or an output. Writing a logic 1 to a DDRD bit enables the output buffer for
the corresponding port D pin; a logic 0 disables the output buffer.
For those devices packaged in a 52-pin LQFP, PTD0–PTD7 are not
connected. DDRD0–DDRD7 should be set to a 1 to configure
PTD0–PTD7 as outputs.
DDRD[7:0] — Data Direction Register D Bits
Avoid glitches on port D pins by writing to the port D data register before
changing data direction register D bits from 0 to 1.
the port D I/O logic.
Reset:
Read:
Write:
KBI[7:4] are input pins to the keyboard interrupt module. The
corresponding control bits, KBIE[7:4], in the keyboard interrupt enable
register, KBIER, select which port pins will be used as a keyboard
interrupt input and overrides any control from the port I/O logic. See
Section 19. Keyboard Interrupt Module (KBI)
These read/write bits control port D data direction. Reset clears
DDRD[7:0], configuring all port D pins as inputs.
1 = Corresponding port D pin configured as output
0 = Corresponding port D pin configured as input
DDRD7
$0007
Bit 7
Figure 17-13. Data Direction Register D (DDRD)
0
Input/Output (I/O) Ports
DDRD6
6
0
DDRD5
5
0
DDRD4
4
0
DDRD3
3
0
DDRD2
Figure 17-14
2
0
Input/Output (I/O) Ports
DDRD1
1
0
Technical Data
shows
DDRD0
Bit 0
0
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