MC908AP16CFAE Freescale Semiconductor, MC908AP16CFAE Datasheet - Page 231
![IC MCU 16K FLASH 8MHZ 48-LQFP](/photos/19/7/190723/4134800_sml.jpg)
MC908AP16CFAE
Manufacturer Part Number
MC908AP16CFAE
Description
IC MCU 16K FLASH 8MHZ 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheets
1.MC908AP8CFBE.pdf
(324 pages)
2.MC908AP16ACFBER.pdf
(316 pages)
3.MC908AP16CFAE.pdf
(322 pages)
Specifications of MC908AP16CFAE
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, IRSCI, SCI, SPI
Peripherals
LED, LVD, POR, PWM
Number Of I /o
32
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
Controller Family/series
HC08
No. Of I/o's
32
Ram Memory Size
1KB
Cpu Speed
8MHz
No. Of Timers
2
Embedded Interface Type
I2C, SCI, SPI
Rohs Compliant
Yes
Processor Series
HC08AP
Core
HC08
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
32
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, DEMO908AP64E, M68CBL05CE
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC908AP16CFAE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC908AP16CFAE
Manufacturer:
FREESCALE
Quantity:
20 000
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in this device clock may not change the state of the SCL line if another device clock is still in its low period.
Therefore the synchronized clock SCL will be held low by the device which last releases SCL to logic high.
Devices with shorter low periods enter a high wait state during this time. When all devices concerned have
counted off their low period, the synchronized SCL line will be released and go high, and all devices will
start counting their high periods. The first device to complete its high period will again pull the SCL line
low.
14.5.8 Handshaking
The clock synchronization mechanism can be used as a handshake in data transfer. A slave device may
hold the SCL low after completion of one byte data transfer and will halt the bus clock, forcing the master
clock into a wait state until the slave releases the SCL line.
14.5.9 Packet Error Code
The packet error code (PEC) for the MMIIC interface is in the form a cyclic redundancy code (CRC). The
PEC is generated by hardware for every transmitted and received byte of data. The transmission of the
generated PEC is controlled by user software.
The CRC data register, MMCRCDR, contains the generated PEC byte, with three other bits in the MMIIC
control registers and status register monitoring and controlling the PEC byte.
14.6 MMIIC I/O Registers
These I/O registers control and monitor MMIIC operation:
Freescale Semiconductor
•
•
•
•
•
•
•
•
Figure 14-3
MMIIC address register (MMADR) — $0048
MMIIC control register 1 (MMCR1) — $0049
MMIIC control register 2 (MMCR2) — $004A
MMIIC status register (MMSR) — $004B
MMIIC data transmit register (MMDTR) — $004C
MMIIC data receive register (MMDRR) — $004D
MMIIC CRC data register (MMCRCDR) — $004E
MMIIC frequency divide register (MMFDR) — $004F
illustrates the clock synchronization waveforms.
SCL1
SCL2
SCL
MC68HC908AP A-Family Data Sheet, Rev. 3
Figure 14-3. Clock Synchronization
Internal counter reset
WAIT
Start counting high period
MMIIC I/O Registers
231
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