MC908GR32AVFAE Freescale Semiconductor, MC908GR32AVFAE Datasheet - Page 238
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MC908GR32AVFAE
Manufacturer Part Number
MC908GR32AVFAE
Description
IC MCU 8BIT 32K FLASH 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC908GR32ACFJE.pdf
(314 pages)
Specifications of MC908GR32AVFAE
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
37
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 24x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
48-LQFP
Controller Family/series
HC08
No. Of I/o's
37
Ram Memory Size
1.5KB
Cpu Speed
8MHz
No. Of Timers
2
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Processor Series
HC08GR
Core
HC08
Data Bus Width
8 bit
Data Ram Size
1.5 KB
Interface Type
ESCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
53
Number Of Timers
8
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, DEMO908GZ60E, M68CBL05CE, M68EML08GPGTE
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 24 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC908GR32AVFAE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Timer Interface Module (TIM1)
ELSxB and ELSxA — Edge/Level Select Bits
TOVx — Toggle-On-Overflow Bit
238
When ELSxB:A = 00, this read/write bit selects the initial output level of the TCHx pin (see
Reset clears the MSxA bit.
When channel x is an input capture channel, these read/write bits control the active edge-sensing logic
on channel x.
When channel x is an output compare channel, ELSxB and ELSxA control the channel x output
behavior when an output compare occurs.
When ELSxB and ELSxA are both clear, channel x is not connected to an I/O port, and pin TCHx is
available as a general-purpose I/O pin.
the ELSxB and ELSxA bits.
When channel x is an output compare channel, this read/write bit controls the behavior of the channel
x output when the TIM1 counter overflows. When channel x is an input capture channel, TOVx has no
effect. Reset clears the TOVx bit.
1 = Initial output level low
0 = Initial output level high
1 = Channel x pin toggles on TIM1 counter overflow.
0 = Channel x pin does not toggle on TIM1 counter overflow.
MSxB
Before changing a channel function by writing to the MSxB or MSxA bit, set
the TSTOP and TRST bits in the TIM1 status and control register (T1SC).
After initially enabling a TIM1 channel register for input capture operation
and selecting the edge sensitivity, clear CHxF to ignore any erroneous
edge detection flags.
X
X
0
0
0
0
0
0
0
1
1
1
MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5
MSxA
X
X
X
0
1
0
0
0
1
1
1
1
Table 17-2. Mode, Edge, and Level Selection
ELSxB
0
0
0
1
1
0
0
1
1
0
1
1
ELSxA
0
0
1
0
1
0
1
0
1
1
0
1
Table 17-2
Output compare
buffered PWM
NOTE
NOTE
Output preset
Input capture
compare or
Buffered
or PWM
output
Mode
shows how ELSxB and ELSxA work. Reset clears
Pin under port control;
initial output level high
Pin under port control;
initial output level low
Capture on rising edge only
Capture on falling edge only
Capture on rising
or falling edge
Software compare only
Toggle output on compare
Clear output on compare
Set output on compare
Toggle output on compare
Clear output on compare
Set output on compare
Configuration
Freescale Semiconductor
Table
17-2).
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