MC908GZ32MFAE Freescale Semiconductor, MC908GZ32MFAE Datasheet - Page 269
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MC908GZ32MFAE
Manufacturer Part Number
MC908GZ32MFAE
Description
IC MCU 8BIT 32K FLASH 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC908GZ60CFJE.pdf
(352 pages)
Specifications of MC908GZ32MFAE
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
CAN, SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
37
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 24x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-LQFP
Controller Family/series
HC08
No. Of I/o's
37
Ram Memory Size
1.5KB
Cpu Speed
8MHz
No. Of Timers
2
Embedded Interface Type
CAN, SCI, SPI
Rohs Compliant
Yes
Processor Series
HC08GZ
Core
HC08
Data Bus Width
8 bit
Data Ram Size
1.5 KB
Interface Type
CAN, ESCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
53
Number Of Timers
8
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, DEMO908GZ60E, M68EML08GZE
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 24 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC908GZ32MFAE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC908GZ32MFAE
Manufacturer:
FREESCALE
Quantity:
20 000
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18.3.4.2 Buffered PWM Signal Generation
Channels 0 and 1 can be linked to form a buffered PWM channel whose output appears on the T1CH0
pin. The TIM1 channel registers of the linked pair alternately control the pulse width of the output.
Setting the MS0B bit in TIM1 channel 0 status and control register (T1SC0) links channel 0 and channel 1.
The TIM1 channel 0 registers initially control the pulse width on the T1CH0 pin. Writing to the TIM1
channel 1 registers enables the TIM1 channel 1 registers to synchronously control the pulse width at the
beginning of the next PWM period. At each subsequent overflow, the TIM1 channel registers (0 or 1) that
control the pulse width are the ones written to last. T1SC0 controls and monitors the buffered PWM
function, and TIM1 channel 1 status and control register (T1SC1) is unused. While the MS0B bit is set,
the channel 1 pin, T1CH1, is available as a general-purpose I/O pin.
18.3.4.3 PWM Initialization
To ensure correct operation when generating unbuffered or buffered PWM signals, use the following
initialization procedure:
Setting MS0B links channels 0 and 1 and configures them for buffered PWM operation. The TIM1
channel 0 registers (TCH0H:TCH0L) initially control the buffered PWM output. TIM1 status control
Freescale Semiconductor
1. In the TIM1 status and control register (T1SC):
2. In the TIM1 counter modulo registers (T1MODH:T1MODL), write the value for the required PWM
3. In the TIM1 channel x registers (T1CHxH:T1CHxL), write the value for the required pulse width.
4. In TIM1 channel x status and control register (T1SCx):
5. In the TIM1 status control register (T1SC), clear the TIM1 stop bit, TSTOP.
period.
a. Stop the TIM1 counter by setting the TIM1 stop bit, TSTOP.
b. Reset the TIM1 counter and prescaler by setting the TIM1 reset bit, TRST.
a. Write 0:1 (for unbuffered output compare or PWM signals) or 1:0 (for buffered output compare
b. Write 1 to the toggle-on-overflow bit, TOVx.
c. Write 1:0 (polarity 1 — to clear output on compare) or 1:1 (polarity 0 — to set output on
or PWM signals) to the mode select bits, MSxB:MSxA. See
compare) to the edge/level select bits, ELSxB:ELSxA. The output action on compare must
force the output to the complement of the pulse width level. See
In buffered PWM signal generation, do not write new pulse width values to
the currently active channel registers. User software should track the
currently active channel to prevent writing a new value to the active
channel. Writing to the active channel registers is the same as generating
unbuffered PWM signals.
In PWM signal generation, do not program the PWM channel to toggle on
output compare. Toggling on output compare prevents reliable 0% duty
cycle generation and removes the ability of the channel to self-correct in the
event of software error or noise. Toggling on output compare can also
cause incorrect PWM signal generation when changing the PWM pulse
width to a new, much larger value.
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
NOTE
NOTE
Table
Table
18-2.
18-2.
Functional Description
269
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