MC9S08DZ128MLL Freescale Semiconductor, MC9S08DZ128MLL Datasheet - Page 263
MC9S08DZ128MLL
Manufacturer Part Number
MC9S08DZ128MLL
Description
MCU 8BIT 128K FLASH 100-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheets
1.MC9S08DV96CLF.pdf
(458 pages)
2.MC9S08DV96CLF.pdf
(4 pages)
3.MC9S08DZ128CLF.pdf
(4 pages)
Specifications of MC9S08DZ128MLL
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, I²C, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
87
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 24x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
100-LQFP
Processor Series
S08DZ
Core
HCS08
Data Bus Width
8 bit
Data Ram Size
8 KB
Interface Type
CAN, I2C, SCI, SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
88
Number Of Timers
3
Operating Supply Voltage
5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMO9S08DZ60
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 24 Channel
Controller Family/series
HCS08
No. Of I/o's
87
Eeprom Memory Size
2KB
Ram Memory Size
8KB
Cpu Speed
40MHz
No. Of Timers
3
Digital Ic Case Style
LQFP
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S08DZ128MLL
Manufacturer:
FREESCAL
Quantity:
300
Company:
Part Number:
MC9S08DZ128MLL
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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The bit time is determined by the oscillator frequency, the baud rate prescaler, and the number of time
quanta (Tq) clock cycles per bit (as shown in
12.3.4.1
A flag can be cleared only by software (writing a 1 to the corresponding bit position) when the condition
which caused the setting is no longer valid. Every flag has an associated interrupt enable bit in the
CANRIER register.
Freescale Semiconductor
Reset:
W
R
1
MSCAN Receiver Flag Register (CANRFLG)
WUPIF
This setting is not valid. Please refer to
TSEG13
Bit Time
1
0
7
This setting is not valid. Please refer to
0
0
0
0
1
1
:
TSEG22
0
0
1
1
:
Figure 12-8. MSCAN Receiver Flag Register (CANRFLG)
= Unimplemented
CSCIF
=
6
0
TSEG12
(
----------------------------------------------------- -
Prescaler value
0
0
0
0
1
1
:
f CANCLK
MC9S08DZ128 Series Data Sheet, Rev. 1
TSEG21
Table 12-7. Time Segment 2 Values
Table 12-8. Time Segment 1 Values
RSTAT1
0
0
1
1
:
0
5
TSEG11
0
0
1
1
1
1
:
Table 12-7
Table 12-35
TSEG20
RSTAT0
)
•
Table 12-35
4
0
0
1
0
1
:
(
1
TSEG10
Chapter 12 Freescale’s Controller Area Network (S08MSCANV1)
+
and
TimeSegment1
0
1
0
1
0
1
:
for valid settings.
TSTAT1
Table
for valid settings.
0
3
Time Segment 2
1 Tq clock cycle
2 Tq clock cycles
7 Tq clock cycles
8 Tq clock cycles
12-8).
15 Tq clock cycles
16 Tq clock cycles
2 Tq clock cycles
3 Tq clock cycles
Time segment 1
1 Tq clock cycle
4 Tq clock cycles
TSTAT0
:
2
0
+
TimeSegment2
:
1
1
OVRIF
1
1
0
1
)
Eqn. 12-1
RXF
0
0
263
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