MC9S08AW48CFUE Freescale Semiconductor, MC9S08AW48CFUE Datasheet - Page 91

• Manufacturer Part Number: MC9S08AW48CFUE
• Description: IC MCU 48K FLASH 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08AW48CFUE

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-QFP
• Processor Series: S08AW
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 6
• Operating Supply Voltage: - 0.3 V to + 5.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMO9S08AW60E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Package: 64PQFP
• Family Name: HCS08
• Maximum Speed: 40 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

1
1
Freescale Semiconductor
Bits 6 through 3 are reserved bits that must always be written to 0.
Bits 6 through 3 are reserved bits that must always be written to 0.
PTASEn
PTADSn
Reset
Reset
7, 2:0
7, 2:0
Field
Field
W
W
R
R
PTASE7
PTADS7
Output Slew Rate Control Enable for Port A Bits — Each of these control bits determine whether output slew
rate control is enabled for the associated PTA pin. For port A pins that are configured as inputs, these bits have
no effect.
0 Output slew rate control disabled for port A bit n.
1 Output slew rate control enabled for port A bit n.
Output Drive Strength Selection for Port A Bits — Each of these control bits selects between low and high
output drive for the associated PTA pin.
0 Low output drive enabled for port A bit n.
1 High output drive enabled for port A bit n.
0
0
7
7
Figure 6-13. Output Slew Rate Control Enable for Port A (PTASE)
Figure 6-14. Output Drive Strength Selection for Port A (PTADS)
R
R
0
0
6
6
Table 6-4. PTASE Register Field Descriptions
Table 6-5. PTADS Register Field Descriptions
MC9S08AC16 Series Data Sheet, Rev. 8
R
R
0
0
5
5
R
R
0
0
4
4
Description
Description
R
R
3
0
3
0
PTASE2
PTADS2
0
0
2
2
Chapter 6 Parallel Input/Output
PTASE1
PTADS1
1
1
0
0
1
1
PTASE0
PTADS0
0
0
0
0
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