C8051F343-GQ Silicon Laboratories Inc, C8051F343-GQ Datasheet - Page 114

• Manufacturer Part Number: C8051F343-GQ
• Description: IC 8051 MCU FLASH 32K 32LQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F34xr

Specifications of C8051F343-GQ

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 32-LQFP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 25
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 21x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051F3x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 2304 B
• Interface Type: I2C, SMBus, SPI, UART, USB
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 25
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 5.25 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: KSK-SL-F34X, KSK-SL-TOOLSTICK, PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F340DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 17 Channel
• Package: 32LQFP
• Device Core: 8051
• Family Name: C8051F34x
• Maximum Speed: 48 MHz
• Data Rom Size: 128 B
• A/d Bit Size: 10 bit
• A/d Channels Available: 17
• Height: 1.4 mm
• Length: 7 mm
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Width: 7 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1748 - ADAPTER TOOLSTICK FOR C8051F34X770-1006 - ISP 4PORT FOR SILABS C8051F MCU
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1301

C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
13. External Data Memory Interface and On-Chip XRAM
4k Bytes (C8051F340/2/4/6/A/C/D) or 2k Bytes (C8051F341/3/5/7/8/9/B) of RAM are included on-chip,
and mapped into the external data memory space (XRAM). The 1k Bytes of USB FIFO space can also be
mapped into XRAM address space for additional general-purpose data storage. Additionally, an External
Memory Interface (EMIF) is available on the C8051F340/1/4/5/8/C devices, which can be used to access
off-chip data memories and memory-mapped devices connected to the GPIO ports. The external memory
space may be accessed using the external move instruction (MOVX) and the data pointer (DPTR), or using
the MOVX indirect addressing mode using R0 or R1. If the MOVX instruction is used with an 8-bit address
operand (such as @R1), then the high byte of the 16-bit address is provided by the External Memory Inter-
face Control Register (EMI0CN, shown in SFR Definition 13.1). Note: the MOVX instruction can also be
used for writing to the FLASH memory. See
MOVX instruction accesses XRAM by default.
13.1. Accessing XRAM
The XRAM memory space is accessed using the MOVX instruction. The MOVX instruction has two forms,
both of which use an indirect addressing method. The first method uses the Data Pointer, DPTR, a 16-bit
register which contains the effective address of the XRAM location to be read from or written to. The sec-
ond method uses R0 or R1 in combination with the EMI0CN register to generate the effective XRAM
address. Examples of both of these methods are given below.
13.1.1. 16-Bit MOVX Example
The 16-bit form of the MOVX instruction accesses the memory location pointed to by the contents of the
DPTR register. The following series of instructions reads the value of the byte at address 0x1234 into the
accumulator A:

The above example uses the 16-bit immediate MOV instruction to set the contents of DPTR. Alternately,
the DPTR can be accessed through the SFR registers DPH, which contains the upper 8-bits of DPTR, and
DPL, which contains the lower 8-bits of DPTR.
13.1.2. 8-Bit MOVX Example
The 8-bit form of the MOVX instruction uses the contents of the EMI0CN SFR to determine the upper 8-bits
of the effective address to be accessed and the contents of R0 or R1 to determine the lower 8-bits of the
effective address to be accessed. The following series of instructions read the contents of the byte at
address 0x1234 into the accumulator A.
114
MOV
MOVX
MOV
MOV
MOVX
DPTR, #1234h
A, @DPTR
EMI0CN, #12h
R0, #34h
a, @R0
; load DPTR with 16-bit address to read (0x1234)
; load contents of 0x1234 into accumulator A
; load high byte of address into EMI0CN
; load low byte of address into R0 (or R1)
; load contents of 0x1234 into accumulator A
Section “12. Flash Memory” on page 107
Rev. 1.3
for details. The