R5F2L387ANFP#U1 Renesas Electronics America, R5F2L387ANFP#U1 Datasheet - Page 737

• Manufacturer Part Number: R5F2L387ANFP#U1
• Description: MCU 1KB FLASH 48K ROM 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/38Ar

Specifications of R5F2L387ANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 68
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 80-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 700 of 802
FMSTP Bit (Flash Memory Stop Bit)
CMDRST Bit (Erase/Write Sequence Reset Bit)
CMDERIE Bit (Erase/Write Error Interrupt Enable Bit)
BSYAEIE Bit (Flash Access Error Interrupt Enable Bit)
RDYSTIE Bit (Flash Ready Status Interrupt Enable Bit)
This bit is used to initialize the flash memory control circuits, and also to reduce the amount of current
consumed by the flash memory. Access to the flash memory is disabled by setting the FMSTP bit to 1.
Write to the FMSTP bit by a program transferred to the RAM.
To reduce the power consumption further in low-speed on-chip oscillator mode (XIN clock stopped) and low-
speed clock mode (XIN clock stopped), set the FMSTP bit to 1. Refer to 9.7.9 Stopping Flash Memory for
details.
When entering stop mode or wait mode while CPU rewrite mode is disabled, the FMR0 register does not need
to be set because the power for the flash memory is automatically turned off and is turned back on when exiting
stop or wait mode.
This bit is used to initialize the flash memory sequence and forcibly stop a program or erase command. The user
ROM area can be read while the flash memory sequence is being initialized.
For addresses and blocks which the program or erase command is forcibly stopped by the CMDRST bit,
execute a block erasure again and ensure it completes normally. If the addresses and blocks which the program
or block erase command is forcibly stopped are allocated in the program area, set the FMR13 bit in the FMR1
register to 1 (lock bit disabled) before executing the block erasure command again.
The time from when the command is forcibly stopped and until reading is enabled is some hundreds s where
the suspend response time is td(SR-SUS).
This bit enables an flash command error interrupt to be generated if a program or block erase error occurs.
When the CMDERIE bit is set to 1 (erase/write error interrupt enabled) and erasure/writing is performed, an
interrupt is generated if an erase or program error occurs.
If a flash command error interrupt is generated, execute the clear status register command during interrupt
handling.
This bit enables a flash access error interrupt to be generated if the flash memory during rewriting is accessed.
This bit enables a flash ready status error interrupt to be generated when the status of the flash memory
sequence changes from the busy to ready status.
Oct 30, 2009
33. Flash Memory