R5F2L3A8ANFP#U1 Renesas Electronics America, R5F2L3A8ANFP#U1 Datasheet - Page 862

MCU 1KB FLASH 64K ROM 100-LQFP

R5F2L3A8ANFP#U1

Manufacturer Part Number
R5F2L3A8ANFP#U1
Description
MCU 1KB FLASH 64K ROM 100-LQFP
Manufacturer
Renesas Electronics America
Series
R8C/Lx/3AAr
Datasheet

Specifications of R5F2L3A8ANFP#U1

Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
LCD, POR, PWM, Voltage Detect, WDT
Number Of I /o
88
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 20x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Supplier Unconfirmed

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5F2L3A8ANFP#U1
Manufacturer:
Renesas Electronics America
Quantity:
135
Company:
Part Number:
R5F2L3A8ANFP#U1
Manufacturer:
Renesas Electronics America
Quantity:
10 000
RENESAS TECHNICAL UPDATE TN-R8C-A007A/E
8.
Notes on bit operation
(This note applies to the R8C/3x Series and R8C/Lx Series.)
Set the following bits with consecutive instructions. Do not allow interrupts or DTC transfer to occur between executing
instructions.
(1) PRC2 bit:
(2) Bits CSPRO, FMR01, FMR02, FMR13, FMR20, FMR22, and FMR27:
(3) Bits FMR14, FMR15, FMR16, and FMR17:
The PRC2 bit becomes 0 after setting it to 1 (write enabled) and writing to an SFR area. Write to the register
protected by the PRC2 bit with the next instruction after that used to set the PRC2 bit to 1. Do not allow interrupts
or DTC transfer between the instruction to set to the PRC2 bit to 1 and the next instruction.
When setting these bits to 1, write 0 immediately followed by 1. Do not allow interrupts and DTC transfer to occur
between writing 0 and writing 1.
When setting these bits to 0, write 1 immediately followed by 0. Do not allow interrupts and DTC transfer to occur
between writing 1 and writing 0.
Date: Sep.25, 2009
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