C8051F019-GQR Silicon Laboratories Inc, C8051F019-GQR Datasheet - Page 72
![IC 8051 MCU 16K FLASH 48TQFP](/photos/15/92/159280/tqfp-48_sml.jpg)
C8051F019-GQR
Manufacturer Part Number
C8051F019-GQR
Description
IC 8051 MCU 16K FLASH 48TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F018r
Specifications of C8051F019-GQR
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
16
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1.25K x 8
Voltage - Supply (vcc/vdd)
2.8 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-TQFP, 48-VQFP
Processor Series
C8051F0x
Core
8051
Data Bus Width
8 bit
Data Ram Size
1.25 KB
Interface Type
I2C, SMBus, SPI, UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
16
Number Of Timers
4 bit
Operating Supply Voltage
2.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F005DK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F019-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
prohibited from reading locations in the lower partition using the MOVC instruction. (Executing a MOVC
instruction from the upper partition with a source address in the lower partition will always return a data value of
0x00.) Software running in the lower partition can access locations in both the upper and lower partition without
restriction.
The Value-added firmware should be placed in the lower partition. On reset, control is passed to the value-added
firmware via the reset vector. Once the value-added firmware completes its initial execution, it branches to a
predetermined location in the upper partition. If entry points are published, software running in the upper partition
may execute program code in the lower partition, but it cannot read the contents of the lower partition. Parameters
may be passed to the program code running in the lower partition either through the typical method of placing them
on the stack or in registers before the call or by placing them in prescribed memory locations in the upper partition.
The SRL address is specified using the contents of the Flash Access Register. The 16-bit SRL address is calculated
as 0xNN00, where NN is the contents of the SRL Security Register. Thus, the SRL can be located on 256-byte
boundaries anywhere in program memory space. However, the 512-byte erase sector size essentially requires that a
512 boundary be used. The contents of a non-initialized SRL security byte is 0x00, thereby setting the SRL address
to 0x0000 and allowing read access to all locations in program memory space by default.
Bits 7-0: FLACL: Flash Access Limit.
R/W
Bit7
This register holds the high byte of the 16-bit program memory read/write/erase limit
address. The entire 16-bit access limit address value is calculated as 0xNN00 where NN is
replaced by contents of FLACL. A write to this register sets the Flash Access Limit. This
register can only be written once after any reset. Any subsequent writes are ignored
until the next reset.
R/W
Bit6
R/W
Bit5
Figure 9.3. FLACL: Flash Access Limit
R/W
Bit4
Rev. 1.2
R/W
Bit3
R/W
Bit2
R/W
Bit1
C8051F018
C8051F019
R/W
Bit0
SFR Address:
Reset Value
00000000
0xB7
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