C8051F043-GQR Silicon Laboratories Inc, C8051F043-GQR Datasheet - Page 308
![no-image](/images/manufacturer_photos/0/6/609/silicon_laboratories_inc_sml.jpg)
C8051F043-GQR
Manufacturer Part Number
C8051F043-GQR
Description
IC 8051 MCU 64K FLASH 64TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F04xr
Specifications of C8051F043-GQR
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
CAN, EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
32
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x8b, 13x10b; D/A 2x10b, 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
For Use With
336-1205 - DEV KIT FOR F040/F041/F042/F043
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F043-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
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C8051F040/1/2/3/4/5/6/7
24.2.1. Edge-triggered Capture Mode
In this mode, a valid transition on the CEXn pin causes PCA0 to capture the value of the PCA0 counter/
timer and load it into the corresponding module's 16-bit capture/compare register (PCA0CPLn and
PCA0CPHn). The CAPPn and CAPNn bits in the PCA0CPMn register are used to select the type of transi-
tion that triggers the capture: low-to-high transition (positive edge), high-to-low transition (negative edge),
or either transition (positive or negative edge). When a capture occurs, the Capture/Compare Flag (CCFn)
in PCA0CN is set to logic 1 and an interrupt request is generated if CCF interrupts are enabled. The CCFn
bit is not automatically cleared by hardware when the CPU vectors to the interrupt service routine, and
must be cleared by software.
Note: The signal at the CEXn pin must be logic high or low for at least two system clock cycles in order for
it to be recognized as valid by the hardware.
306
Port I/O
Crossbar
Figure 24.4. PCA Capture Mode Diagram
CEXn
W
P
M
1
6
n
PCA0CPMn
O
M
E
C
n
Rev. 1.5
C
A
P
P
n
C
A
P
N
n
0
1
M
A
T
n
T
O
G
n
W
M
P
n
E
C
C
F
n
0
1
C
F
C
R
PCA0CN
C
C
F
5
C
C
F
4
PCA
Timebase
C
C
F
3
C
C
F
2
C
C
F
1
PCA Interrupt
C
C
F
0
Capture
PCA0CPLn
PCA0L
PCA0CPHn
PCA0H
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