C8051F012-GQ Silicon Laboratories Inc, C8051F012-GQ Datasheet - Page 126

• Manufacturer Part Number: C8051F012-GQ
• Description: IC 8051 MCU 32K FLASH 32LQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F01xr

Specifications of C8051F012-GQ

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 32-LQFP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 4x10b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051F0x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: I2C, SMBus, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 8
• Number Of Timers: 4 bit
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F005DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 4 Channel
• On-chip Dac: 12 bit, 2 Channel
• Data Rom Size: 32 KB
• A/d Bit Size: 10 bit
• A/d Channels Available: 4
• Height: 1.4 mm
• Length: 7 mm
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Width: 7 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1193

in an “off-line” state. In a multiple-master environment, the system controller should check the state of the
SLVSEL flag (SPI0CN.2) to ensure the bus is free before setting the MSTEN bit and initiating a data transfer.
17.3.
As shown in Figure 17.4, four combinations of serial clock phase and polarity can be selected using the clock
control bits in the SPI Configuration Register (SPI0CFG). The CKPHA bit (SPI0CFG.7) selects one of two clock
phases (edge used to latch the data). The CKPOL bit (SPI0CFG.6) selects between an active-high or active-low
clock. Both master and slave devices must be configured to use the same clock phase and polarity. Note: the SPI
should be disabled (by clearing the SPIEN bit, SPI0CN.0) while changing the clock phase and polarity.
The SPI Clock Rate Register (SPI0CKR) as shown in Figure 17.7 controls the master mode serial clock frequency.
This register is ignored when operating in slave mode.
Serial Clock Timing
MISO/MOSI
SCK
(CKPOL = 0, CKPHA = 0)
SCK
(CKPOL = 0, CKPHA = 1)
SCK
(CKPOL = 1, CKPHA = 0)
SCK
(CKPOL = 1, CKPHA = 1)
NSS
Figure 17.4. Data/Clock Timing Diagram
MSB
Bit 6
Rev. 1.7
Bit 5
Bit 4
Bit 3
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Bit 2
Bit 1
LSB
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