MCF5270CVM150J Freescale Semiconductor, MCF5270CVM150J Datasheet - Page 96
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MCF5270CVM150J
Manufacturer Part Number
MCF5270CVM150J
Description
IC MCU 166MHZ 256MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Specifications of MCF5270CVM150J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
150MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, WDT
Number Of I /o
97
Program Memory Type
ROMless
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
196-MAPBGA
Processor Series
MCF527x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5270CVM150J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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ColdFire Core
STRLDSR
Operation:
Assembler Syntax:STRLDSR #<data>
Attributes:
Description: Pushes the contents of the Status Register onto the stack and then reloads the
Status Register with the immediate data value. This instruction is intended for use as the first
instruction of an interrupt service routine shared across multiple interrupt request levels. It allows
the level of the just-taken interrupt request to be stored in memory (using the SR[IML] field), and
then masks interrupts by loading the SR[IML] field with 0x7 (if desired). If execution is attempted
with bit 13 of the immediate data cleared (attempting to place the processor in user mode), a
privilege violation exception is generated. The opcode for STRLDSR is 0x40E7 46FC.
Condition
Codes:
3-30
Instruction
Format:
Opcode present
STRLDSR
X
∗
15
0
0
N
∗
14
1
1
If Supervisor State
Then SP - 4 → SP; zero-filled SR → (SP); immediate data → SR
Else TRAP
Size = word
Z
∗
13
0
0
Store/Load Status Register
(Supported Starting with ISA A+)
12
V
∗
0
0
MCF5271 Reference Manual, Rev. 2
V2, V3 Core (ISA_A)
11
0
0
C
∗
No
10
0
1
X Set to the value of bit 4 of the immediate operand
N Set to the value of bit 3 of the immediate operand
Z Set to the value of bit 2 of the immediate operand
V Set to the value of bit 1 of the immediate operand
C Set to the value of bit 0 of the immediate operand
0
1
9
Immediate Data
0
0
8
V4 Core (ISA_B)
1
1
7
No
1
1
6
5
1
1
STRLDSR
4
0
1
V2 Core (ISA_A+)
3
0
1
Freescale Semiconductor
Yes
2
1
1
1
1
0
1
0
0
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