R5F363AENFA#U0 Renesas Electronics America, R5F363AENFA#U0 Datasheet - Page 101

• Manufacturer Part Number: R5F363AENFA#U0
• Description: MCU 4KB FLASH 256/16K 100-QFP
• Manufacturer: Renesas Electronics America
• Series: M16C/60/63r

Specifications of R5F363AENFA#U0

• Core Processor: M16C/60
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, I²C, SIO, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 20K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M16C/63 Group
REJ03B0271-0100 Rev.1.00 Sep 15, 2009
Page 99 of 113
Figure 5.31
Memory Expansion Mode and Microprocessor Mode
(in 2 or 3 waits setting, and when accessing external area and using multiplexed bus )
Read timing
Write timing
BCLK
CSi
ADi
/DBi
ADi
BHE
ALE
RD
BCLK
CSi
ADi
/DBi
ADi
BHE
ALE
WR,WRL,
WRH
t
Measuring conditions
cyc
V
Input timing voltage: V = 0.6 V, V
Output timing voltage: V = 1.5 V, V
Timing Diagram
CC1
=
f
= V
(BCLK)
1
CC2
= 3 V
(0.5 × t
t
25ns(max.)
(0.5 × t
d(BCLK-ALE)
t
t
25ns(max.)
t
d(AD-ALE)
50ns(max.)
t
d(BCLK-ALE)
d(BCLK-CS)
50ns(max.)
d(BCLK-AD)
t
t
50ns(max.)
50ns(max.)
d(BCLK-AD)
cyc
d(BCLK-CS)
t
d(AD-ALE)
cyc
-40ns(min.)
IL
-40ns(min.)
OL
Address
Address
t
-4ns(min.)
h(BCLK-ALE)
t
-4ns(min.)
h(BCLK-ALE)
IH
(0.5 × t
t
t
0ns(min.)
d(AD-RD)
h(ALE-AD)
OH
= 2.4 V
cyc
= 1.5 V
-15ns(min.)
t
40ns(max.)
t
50ns(max.)
d(BCLK-RD)
d(BCLK-DB)
40ns(max.)
t
d(BCLK-WR)
t
0ns(min.)
d(AD-WR)
t
8ns(max.)
dz(RD-AD)
t
cyc
t
cyc
{(n-0.5) × t
Data output
{(n-0.5) × t
t
ac3(RD-DB)
t
d(DB-WR)
n: 2 (when 2 waits)
cyc
cyc
3 (when 3 waits)
-60}ns(max.)
-50}ns(min.)
t
50ns(min.)
su(DB-RD)
Data input
(0.5 × t
(0.5 × t
V
CC1
cyc
cyc
(0.5 × t
t
(0.5 × t
t
t
0ns(min.)
h(RD-CS)
h(WR-CS)
h(BCLK-WR)
5. Electrical Characteristics
(0.5 × t
-10)ns(min.)
t
-10)ns(min.)
t
h(RD-AD)
0ns(min.)
t
h(BCLK-RD)
t
h(WR-DB)
t
h(WR-AD)
0ns(min.)
h(RD-DB)
= V
cyc
cyc
cyc
-10)ns(min.)
-10)ns(min.)
-10)ns(min.)
CC2
t
0ns(min.)
t
t
t
h(BCLK-CS)
0ns(min.)
0ns(min.)
0ns(min.)
t
h(BCLK-AD)
h(BCLK-DB)
h(BCLK-AD)
0ns(min.)
h(BCLK-CS)
Address
Address
= 3 V