MCF52255CAF80 Freescale Semiconductor, MCF52255CAF80 Datasheet - Page 37
![MCU 32BIT COLDFIRE V2 100LQFP](/photos/12/39/123950/mcf52255caf80_sml.jpg)
MCF52255CAF80
Manufacturer Part Number
MCF52255CAF80
Description
MCU 32BIT COLDFIRE V2 100LQFP
Manufacturer
Freescale Semiconductor
Series
MCF5225xr
Datasheet
1.MCF52256CAG66.pdf
(46 pages)
Specifications of MCF52255CAF80
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
80MHz
Connectivity
CAN, Ethernet, I²C, QSPI, UART/USART, USB OTG
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
56
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Processor Series
MCF522x
Core
ColdFire V2
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
QSPI, I2C, UART
Maximum Clock Frequency
80 MHz
Number Of Programmable I/os
56
Number Of Timers
4
Operating Supply Voltage
- 0.3 V to + 4 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
TWR-MCF5225X, TWR-SENSOR-PAK, TWR-SER, TWR-ELEV, TOWER, M52259EVB, M52259DEMOKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Electrical Characteristics
2.14
Table 23
Table 24
37
lists specifications for the I
lists specifications for the I
Num
1
2
3
I
11
I2
I3
I4
I5
I6
I7
I8
I9
2
Num
Output numbers depend on the value programmed into the IFDR; an IFDR programmed with the
maximum frequency (IFDR = 0x20) results in minimum output timings as shown in
interface is designed to scale the actual data transition time to move it to the middle of the SCL low
period. The actual position is affected by the prescale and division values programmed into the IFDR;
however, the numbers given in
Because SCL and SDA are open-collector-type outputs, which the processor can only actively drive
low, the time SCL or SDA take to reach a high level depends on external signal capacitance and pull-up
resistor values.
Specified at a nominal 50-pF load.
C Input/Output Timing Specifications
11
I2
I3
I4
I5
I6
I7
I8
I9
1
2
1
3
1
1
1
1
1
Start condition hold time
Clock low period
SCL/SDA rise time (V
Data hold time
SCL/SDA fall time (V
Clock high time
Data setup time
Start condition setup time (for repeated start condition only)
Stop condition setup time
Table 24. I
Table 23. I
Start condition hold time
Clock low period
I2C_SCL/I2C_SDA rise time
(V
Data hold time
I2C_SCL/I2C_SDA fall time
(V
Clock high time
Data setup time
Start condition setup time (for repeated start
condition only)
Stop condition setup time
IL
IH
= 0.5 V to V
= 2.4 V to V
2
2
C Output Timing Specifications between I2C_SCL and I2C_SDA
C Input Timing Specifications between I2C_SCL and I2C_SDA
2
2
C input timing parameters shown in
C output timing parameters shown in
IH
IL
Characteristic
IH
IL
= 2.4 V)
= 0.5 V)
MCF52259 ColdFire Microcontroller, Rev. 4
Characteristic
= 2.4 V to V
= 0.5 V to V
Table 24
IL
IH
are minimum values.
= 0.5 V)
= 2.4 V)
Figure
10 t
10 t
20 t
10 t
Figure
6 t
7 t
2 t
Min
—
—
CYC
CYC
CYC
CYC
CYC
CYC
CYC
13.
13.
2 t
2 t
8 t
4 t
2 t
Min
—
—
0
0
CYC
CYC
CYC
CYC
CYC
Max
—
—
—
—
—
—
—
—
3
Table
Max
—
—
—
—
—
—
—
1
1
Freescale Semiconductor
24. The I
Units
ns
ns
s
ns
ns
ns
ns
ns
ns
Units
ms
ms
ns
ns
ns
ns
ns
ns
ns
2
C