C8051F023-GQR Silicon Laboratories Inc, C8051F023-GQR Datasheet
C8051F023-GQR
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C8051F023-GQR Summary of contents
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ANALOG PERIPHERALS - SAR ADC • 12-Bit (C8051F020/1) • 10-Bit (C8051F022/3) • ± 1 LSB INL • Programmable Throughput up to 100 ksps • External Inputs; Programmable as Single-Ended or Differential • Programmable Amplifier Gain: 16, 8, ...
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C8051F020/1/2/3 2 Notes Rev. 1.4 ...
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TABLE OF CONTENTS 1. SYSTEM OVERVIEW .........................................................................................................17 1.1. CIP-51™ Microcontroller Core ......................................................................................22 1.1.1. Fully 8051 Compatible ..........................................................................................22 1.1.2. Improved Throughput ............................................................................................22 1.1.3. Additional Features................................................................................................23 1.2. On-Chip Memory ............................................................................................................24 1.3. JTAG Debug and Boundary Scan ...................................................................................25 1.4. Programmable Digital I/O and ...
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C8051F020/1/2/3 10. VOLTAGE REFERENCE (C8051F021/3)..........................................................................93 11. COMPARATORS..................................................................................................................95 12. CIP-51 MICROCONTROLLER........................................................................................101 12.1.Instruction Set................................................................................................................102 12.1.1. Instruction and CPU Timing................................................................................102 12.1.2. MOVX Instruction and Program Memory...........................................................102 12.2.Memory Organization ...................................................................................................107 12.2.1. Program Memory .................................................................................................107 12.2.2. Data Memory .......................................................................................................108 12.2.3. General Purpose Registers ...................................................................................108 12.2.4. ...
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Accessing XRAM..........................................................................................................145 16.1.1. 16-Bit MOVX Example.......................................................................................145 16.1.2. 8-Bit MOVX Example.........................................................................................145 16.2.Configuring the External Memory Interface .................................................................146 16.3.Port Selection and Configuration ..................................................................................146 16.4. Multiplexed and Non-multiplexed Selection.................................................................148 16.4.1. Multiplexed Configuration ..................................................................................148 16.4.2. Non-multiplexed Configuration...........................................................................149 16.5.Memory Mode Selection ...............................................................................................150 16.5.1. Internal ...
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C8051F020/1/2/3 18.3.SMBus Transfer Modes.................................................................................................187 18.3.1. Master Transmitter Mode ....................................................................................187 18.3.2. Master Receiver Mode.........................................................................................187 18.3.3. Slave Transmitter Mode.......................................................................................188 18.3.4. Slave Receiver Mode ...........................................................................................188 18.4.SMBus Special Function Registers ...............................................................................189 18.4.1. Control Register ...................................................................................................189 18.4.2. Clock Rate Register .............................................................................................192 18.4.3. Data Register........................................................................................................193 18.4.4. ...
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Mode 2: Baud Rate Generator .............................................................................237 22.3.Timer 3 .......................................................................................................................240 22.4.Timer 4 .......................................................................................................................243 22.4.1. Mode 0: 16-bit Counter/Timer with Capture .......................................................244 22.4.2. Mode 1: 16-bit Counter/Timer with Auto-Reload ...............................................245 22.4.3. Mode 2: Baud Rate Generator .............................................................................246 23. PROGRAMMABLE COUNTER ARRAY ...
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C8051F020/1/2/3 8 Notes Rev. 1.4 ...
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... Product Selection Guide ......................................................................................17 Figure 1.1. C8051F020 Block Diagram.................................................................................18 Figure 1.2. C8051F021 Block Diagram.................................................................................19 Figure 1.3. C8051F022 Block Diagram.................................................................................20 Figure 1.4. C8051F023 Block Diagram.................................................................................21 Figure 1.5. Comparison of Peak MCU Execution Speeds.....................................................22 Figure 1.6. On-Board Clock and Reset..................................................................................23 Figure 1.7. On-Chip Memory Map ........................................................................................24 Figure 1 ...
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C8051F020/1/2/3 Figure 5.17. 12-Bit ADC0 Window Interrupt Example: Right Justified Differential Data.....55 Figure 5.18. 12-Bit ADC0 Window Interrupt Example: Left Justified Single-Ended Data....56 Figure 5.19. 12-Bit ADC0 Window Interrupt Example: Left Justified Differential Data.......57 Table 5.1. 12-Bit ADC0 Electrical Characteristics ...
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Figure 9.1. Voltage Reference Functional Block Diagram....................................................91 Figure 9.2. REF0CN: Reference Control Register ................................................................92 Table 9.1. Voltage Reference Electrical Characteristics ......................................................92 10. VOLTAGE REFERENCE (C8051F021/3)..........................................................................93 Figure 10.1. Voltage Reference Functional Block Diagram ...................................................93 Figure 10.2. REF0CN: Reference Control Register ................................................................94 ...
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C8051F020/1/2/3 Table 15.1. FLASH Electrical Characteristics .....................................................................140 Figure 15.1. FLASH Program Memory Map and Security Bytes .........................................141 Figure 15.2. FLACL: FLASH Access Limit .........................................................................142 Figure 15.3. FLSCL: FLASH Memory Control ....................................................................143 Figure 15.4. PSCTL: Program Store Read/Write Control .....................................................144 16. ...
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SYSTEM MANAGEMENT BUS / I2C BUS (SMBUS0) .................................................183 Figure 18.1. SMBus0 Block Diagram ...................................................................................183 Figure 18.2. Typical SMBus Configuration ..........................................................................184 Figure 18.3. SMBus Transaction ...........................................................................................185 Figure 18.4. Typical Master Transmitter Sequence...............................................................187 Figure 18.5. Typical Master Receiver Sequence ...................................................................187 Figure ...
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C8051F020/1/2/3 Figure 21.7. UART Multi-Processor Mode Interconnect Diagram .......................................220 Table 21.2. Oscillator Frequencies for Standard Baud Rates...............................................222 Figure 21.8. SCON1: UART1 Control Register....................................................................223 Figure 21.9. SBUF1: UART1 Data Buffer Register..............................................................224 Figure 21.10. SADDR1: UART1 Slave Address Register ....................................................224 Figure 21.11. ...
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Figure 23.4. PCA Capture Mode Diagram ............................................................................253 Figure 23.5. PCA Software Timer Mode Diagram................................................................254 Figure 23.6. PCA High Speed Output Mode Diagram ..........................................................255 Figure 23.7. PCA Frequency Output Mode ...........................................................................256 Figure 23.8. PCA 8-Bit PWM Mode Diagram ......................................................................257 Figure 23.9. ...
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C8051F020/1/2/3 16 Notes Rev. 1.4 ...
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... Figure 1.2 and Figure 1.4). Table 1.1. Product Selection Guide C8051F020 25 64k 4352 C8051F021 25 64k 4352 C8051F022 25 64k 4352 C8051F023 25 64k 4352 C8051F020/1/2/3 2 ...
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C8051F020/1/2/3 Figure 1.1. C8051F020 Block Diagram VDD VDD VDD Digital Power DGND DGND DGND AV+ AV+ Analog Power AGND AGND TCK Boundary Scan JTAG TMS TDI Logic Debug HW TDO Reset /RST VDD WDT MONEN Monitor External XTAL1 Oscillator XTAL2 ...
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Figure 1.2. C8051F021 Block Diagram VDD VDD VDD Digital Power DGND DGND DGND AV+ Analog Power AGND TCK Boundary Scan JTAG TMS Logic TDI Debug HW TDO Reset /RST VDD WDT MONEN Monitor External XTAL1 Oscillator XTAL2 Circuit System Clock ...
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C8051F020/1/2/3 Figure 1.3. C8051F022 Block Diagram VDD VDD VDD Digital Power DGND DGND DGND AV+ AV+ Analog Power AGND AGND TCK Boundary Scan JTAG TMS Logic TDI Debug HW TDO Reset /RST VDD WDT MONEN Monitor External XTAL1 Oscillator XTAL2 ...
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... Figure 1.4. C8051F023 Block Diagram VDD VDD VDD Digital Power DGND DGND DGND AV+ Analog Power AGND TCK Boundary Scan JTAG TMS Logic TDI Debug HW TDO Reset /RST VDD WDT MONEN Monitor External XTAL1 Oscillator XTAL2 Circuit System Clock Internal Oscillator VREF ...
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C8051F020/1/2/3 1.1. CIP-51™ Microcontroller Core 1.1.1. Fully 8051 Compatible The C8051F020 family utilizes Silicon Labs' proprietary CIP-51 microcontroller core. The CIP-51 is fully compati- ble with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop ...
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Additional Features The C8051F020 MCU family includes several key enhancements to the CIP-51 core and peripherals to improve over- all performance and ease of use in end applications. The extended interrupt handler provides 22 interrupt sources into the CIP-51 ...
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C8051F020/1/2/3 1.2. On-Chip Memory The CIP-51 has a standard 8051 program and data address configuration. It includes 256 bytes of data RAM, with the upper 128 bytes dual-mapped. Indirect addressing accesses the upper 128 bytes of general purpose RAM, and ...
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JTAG Debug and Boundary Scan The C8051F020 family has on-chip JTAG boundary scan and debug circuitry that provides non-intrusive, full speed, in-circuit debugging using the production part installed in the end application, via the four-pin JTAG interface. The JTAG ...
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C8051F020/1/2/3 1.4. Programmable Digital I/O and Crossbar The standard 8051 Ports ( and 3) are available on the MCUs. The C8051F020/2 have 4 additional ports ( and 7) for a total of 64 general-purpose port I/O. ...
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Programmable Counter Array The C8051F020 MCU family includes an on-board Programmable Counter/Timer Array (PCA) in addition to the five 16-bit general purpose counter/timers. The PCA consists of a dedicated 16-bit counter/timer time base with 5 pro- grammable capture/compare modules. ...
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C8051F020/1/2/3 1.7. 12-Bit Analog to Digital Converter The C8051F020/1 has an on-chip 12-bit SAR ADC (ADC0) with a 9-channel input multiplexer and programmable gain amplifier. With a maximum throughput of 100 ksps, the ADC offers true 12-bit accuracy with an ...
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Analog to Digital Converter The C8051F020/1/2/3 has an on-board 8-bit SAR ADC (ADC1) with an 8-channel input multiplexer and programma- ble gain amplifier. This ADC features a 500 ksps maximum throughput and true 8-bit accuracy with an INL ...
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C8051F020/1/2/3 1.9. Comparators and DACs Each C8051F020/1/2/3 MCU has two 12-bit DACs and two comparators on chip. The MCU data and control inter- face to each comparator and DAC is via the Special Function Registers. The MCU can place any ...
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ABSOLUTE MAXIMUM RATINGS Table 2.1. Absolute Maximum Ratings PARAMETER Ambient temperature under bias Storage Temperature Voltage on any Pin (except VDD and Port I/O) with respect to DGND Voltage on any Port I/O Pin or /RST with respect to ...
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C8051F020/1/2/3 3. GLOBAL DC ELECTRICAL CHARACTERISTICS Table 1.1. Global DC Electrical Characteristics -40°C to +85°C, 25 MHz System Clock unless otherwise specified. PARAMETER Analog Supply Voltage Analog Supply Current AV+=2.7 V, Internal REF, ADC, DAC, Comparators all active Analog Supply ...
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PINOUT AND PACKAGE DEFINITIONS Pin Numbers Name F020 F021 F022 F023 VDD 37, 64, 24, 41 DGND 38, 63, 25, 40 AV+ 11 AGND 10 TMS 1 58 TCK 2 59 ...
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C8051F020/1/2/3 Pin Numbers Name F020 F021 F022 F023 AIN0 AIN0 AIN0 AIN0 AIN0 AIN0 AIN0 AIN0 CP0 CP0 CP1+ 7 ...
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Pin Numbers Name F020 F021 F022 F023 /RD/P0 /WR/P0 AIN1.0/A8/P1 AIN1.1/A9/P1 AIN1.2/A10/P1 AIN1.3/A11/P1 AIN1.4/A12/P1 AIN1.5/A13/P1 AIN1.6/A14/P1 AIN1.7/A15/P1 A8m/A0/P2 ...
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C8051F020/1/2/3 Pin Numbers Name F020 F021 F022 F023 A14m/A6/P2 A15m/A7/P2 AD0/D0/P3 AD1/D1/P3 AD2/D2/P3 AD3/D3/P3 AD4/D4/P3 AD5/D5/P3 AD6/D6/P3.6/IE6 48 39 AD7/D7/P3.7/IE7 47 38 P4.0 98 ...
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Pin Numbers Name F020 F021 Type F022 F023 A11/P5 I/O Port 5.3. See Port Input/Output section for complete description. A12/P5 I/O Port 5.4. See Port Input/Output section for complete description. A13/P5 I/O Port 5.5. ...
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C8051F020/1/2/3 Figure 4.1. TQFP-100 Pinout Diagram TMS 1 TCK 2 TDI 3 TDO 4 /RST 5 CP1- 6 CP1+ 7 CP0- 8 CP0+ 9 AGND 10 AV+ 11 VREF 12 AGND 13 AV+ 14 VREFD 15 VREF0 16 VREF1 17 ...
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Figure 4.2. TQFP-100 Package Drawing 100 PIN 1 DESIGNATOR Rev. 1.4 C8051F020/1/2/3 MIN NOM MAX (mm) (mm) (mm 1.20 A1 0.05 - 0.15 A2 0.95 1.00 1.05 b ...
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... Figure 4.3. TQFP-64 Pinout Diagram CP1- 1 CP1+ 2 CP0- 3 CP0+ 4 AGND 5 AV+ 6 VREF 7 VREFA 8 AIN0.0 9 AIN0.1 10 AIN0.2 11 AIN0.3 12 AIN0.4 13 AIN0.5 14 AIN0.6 15 AIN0 C8051F021 C8051F023 Rev. 1.4 48 /WR/P0.7 47 AD0/D0/P3.0 46 AD1/D1/P3.1 45 AD2/D2/P3.2 44 AD3/D3/P3.3 43 AD4/D4/P3.4 42 AD5/D5/P3.5 41 VDD 40 DGND 39 AD6/D6/P3.6/IE6 38 AD7/D7/P3.7/IE7 37 A8m/A0/P2.0 36 A9m/A1/P2.1 35 A10m/A2/P2.2 34 A11m/A3/P2.3 33 A12m/A4/P2.4 ...
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Figure 4.4. TQFP-64 Package Drawing PIN 1 DESIGNATOR Rev. 1.4 C8051F020/1/2/3 MIN NOM MAX (mm) (mm) (mm 1.20 A1 0.05 - 0.15 A2 0.95 - 1.05 ...
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C8051F020/1/2/3 42 Notes Rev. 1.4 ...
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ADC0 (12-BIT ADC, C8051F020/1 ONLY) The ADC0 subsystem for the C8051F020/1 consists of a 9-channel, configurable analog multiplexer (AMUX0), a programmable gain amplifier (PGA0), and a 100 ksps, 12-bit successive-approximation-register ADC with integrated track-and-hold and Programmable Window Detector (see ...
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C8051F020/1 The Temperature Sensor transfer function is shown in Figure 5.2. The output voltage (V the Temperature Sensor is selected by bits AMX0AD3-0 in register AMX0SL; this voltage will be amplified by the PGA according to the user-programmed PGA settings. ...
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Tracking Modes The AD0TM bit in register ADC0CN controls the ADC0 track-and-hold mode. In its default state, the ADC0 input is continuously tracked when a conversion is not in progress. When the AD0TM bit is logic 1, ADC0 operates ...
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C8051F020/1 5.2.3. Settling Time Requirements When the ADC0 input configuration is changed (i.e., a different MUX or PGA selection is made), a minimum settling (or tracking) time is required before an accurate conversion can be performed. This settling time is ...
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Figure 5.5. AMX0CF: AMUX0 Configuration Register (C8051F020/1) R/W R/W R Bit7 Bit6 Bit5 Bits7-4: UNUSED. Read = 0000b; Write = don’t care Bit3: AIN67IC: AIN6, AIN7 Input Pair Configuration Bit 0: AIN6 and AIN7 are independent single-ended ...
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C8051F020/1 Figure 5.6. AMX0SL: AMUX0 Channel Select Register (C8051F020/1) R/W R/W R Bit7 Bit6 Bit5 Bits7-4: UNUSED. Read = 0000b; Write = don’t care Bits3-0: AMX0AD3-0: AMX0 Address Bits 0000-1111b: ADC Inputs selected per chart below 0000 ...
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Figure 5.7. ADC0CF: ADC0 Configuration Register (C8051F020/1) R/W R/W R/W AD0SC4 AD0SC3 AD0SC2 Bit7 Bit6 Bit5 Bits7-3: AD0SC4-0: ADC0 SAR Conversion Clock Period Bits SAR Conversion clock is derived from system clock by the following equation, where AD0SC refers to ...
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C8051F020/1 Figure 5.8. ADC0CN: ADC0 Control Register (C8051F020/1) R/W R/W R/W AD0EN AD0TM AD0INT AD0BUSY AD0CM1 AD0CM0 Bit7 Bit6 Bit5 Bit7: AD0EN: ADC0 Enable Bit. 0: ADC0 Disabled. ADC0 is in low-power shutdown. 1: ADC0 Enabled. ADC0 is active and ...
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Figure 5.9. ADC0H: ADC0 Data Word MSB Register (C8051F020/1) R/W R/W R/W Bit7 Bit6 Bit5 Bits7-0: ADC0 Data Word High-Order Bits. For AD0LJST = 0: Bits 7-4 are the sign extension of Bit3. Bits 3-0 are the upper 4 bits ...
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C8051F020/1 Figure 5.11. ADC0 Data Word Example (C8051F020/1) 12-bit ADC0 Data Word appears in the ADC0 Data Word Registers as follows: ADC0H[3:0]:ADC0L[7:0], if AD0LJST = 0 (ADC0H[7:4] will be sign-extension of ADC0H.3 for a differential reading, otherwise = 0000b). ADC0H[7:0]:ADC0L[7:4], ...
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ADC0 Programmable Window Detector The ADC0 Programmable Window Detector continuously compares the ADC0 output to user-programmed limits, and notifies the system when an out-of-bound condition is detected. This is especially effective in an interrupt-driven system, saving code space and ...
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C8051F020/1 Figure 5.16. 12-Bit ADC0 Window Interrupt Example: Right Justified Single-Ended Data Input Voltage ADC Data (AD0 - AGND) Word REF x (4095/4096) 0x0FFF AD0WINT not affected 0x0201 REF x (512/4096) 0x0200 ADC0LTH:ADC0LTL 0x01FF AD0WINT=1 0x0101 REF x (256/4096) 0x0100 ...
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Figure 5.17. 12-Bit ADC0 Window Interrupt Example: Right Justified Differential Data Input Voltage ADC Data (AD0 - AD1) Word REF x (2047/2048) 0x07FF AD0WINT not affected 0x0101 REF x (256/2048) 0x0100 ADC0LTH:ADC0LTL 0x00FF AD0WINT=1 0x0000 REF x (-1/2048) 0xFFFF ADC0GTH:ADC0GTL ...
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C8051F020/1 Figure 5.18. 12-Bit ADC0 Window Interrupt Example: Left Justified Single-Ended Data Input Voltage ADC Data (AD0 - AGND) Word REF x (4095/4096) 0xFFF0 AD0WINT not affected 0x2010 REF x (512/4096) 0x2000 ADC0LTH:ADC0LTL 0x1FF0 AD0WINT=1 0x1010 REF x (256/4096) 0x1000 ...
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Figure 5.19. 12-Bit ADC0 Window Interrupt Example: Left Justified Differential Data Input Voltage ADC Data (AD0 - AD1) Word REF x (2047/2048) 0x7FF0 AD0WINT not affected 0x1010 REF x (256/2048) 0x1000 ADC0LTH:ADC0LTL 0x0FF0 AD0WINT=1 0x0000 REF x (-1/2048) 0xFFF0 ADC0GTH:ADC0GTL ...
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C8051F020/1 Table 5.1. 12-Bit ADC0 Electrical Characteristics (C8051F020/1) VDD = 3.0V, AV+ = 3.0V, VREF = 2.40V (REFBE=0), PGA Gain = 1, -40°C to +85°C unless otherwise specified PARAMETER DC ACCURACY Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Full Scale ...
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ADC0 (10-BIT ADC, C8051F022/3 ONLY) The ADC0 subsystem for the C8051F022/3 consists of a 9-channel, configurable analog multiplexer (AMUX0), a programmable gain amplifier (PGA0), and a 100 ksps, 10-bit successive-approximation-register ADC with integrated track-and-hold and Programmable Window Detector (see ...
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C8051F022/3 The Temperature Sensor transfer function is shown in Figure 6.2. The output voltage (V the Temperature Sensor is selected by bits AMX0AD3-0 in register AMX0SL; this voltage will be amplified by the PGA according to the user-programmed PGA settings. ...
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Tracking Modes The AD0TM bit in register ADC0CN controls the ADC0 track-and-hold mode. In its default state, the ADC0 input is continuously tracked when a conversion is not in progress. When the AD0TM bit is logic 1, ADC0 operates ...
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C8051F022/3 6.2.3. Settling Time Requirements When the ADC0 input configuration is changed (i.e., a different MUX or PGA selection is made), a minimum settling (or tracking) time is required before an accurate conversion can be performed. This settling time is ...
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Figure 6.5. AMX0CF: AMUX0 Configuration Register (C8051F022/3) R/W R/W R Bit7 Bit6 Bit5 Bits7-4: UNUSED. Read = 0000b; Write = don’t care Bit3: AIN67IC: AIN6, AIN7 Input Pair Configuration Bit 0: AIN6 and AIN7 are independent single-ended ...
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C8051F022/3 Figure 6.6. AMX0SL: AMUX0 Channel Select Register (C8051F022/3) R/W R/W R Bit7 Bit6 Bit5 Bits7-4: UNUSED. Read = 0000b; Write = don’t care Bits3-0: AMX0AD3-0: AMX0 Address Bits 0000-1111b: ADC Inputs selected per chart below 0000 ...
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Figure 6.7. ADC0CF: ADC0 Configuration Register (C8051F022/3) R/W R/W R/W AD0SC4 AD0SC3 AD0SC2 Bit7 Bit6 Bit5 Bits7-3: AD0SC4-0: ADC0 SAR Conversion Clock Period Bits SAR Conversion clock is derived from system clock by the following equation, where AD0SC refers to ...
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C8051F022/3 Figure 6.8. ADC0CN: ADC0 Control Register (C8051F022/3) R/W R/W R/W AD0EN AD0TM AD0INT AD0BUSY AD0CM1 AD0CM0 Bit7 Bit6 Bit5 Bit7: AD0EN: ADC0 Enable Bit. 0: ADC0 Disabled. ADC0 is in low-power shutdown. 1: ADC0 Enabled. ADC0 is active and ...
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Figure 6.9. ADC0H: ADC0 Data Word MSB Register (C8051F022/3) R/W R/W R/W Bit7 Bit6 Bit5 Bits7-0: ADC Data Word High-Order Bits. For ADLJST = 0: Bits 7-2 are the sign extension of Bit1. Bits 1-0 are the upper 2 bits ...
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C8051F022/3 Figure 6.11. ADC0 Data Word Example (C8051F022/3) 10-bit ADC Data Word appears in the ADC Data Word Registers as follows: ADC0H[1:0]:ADC0L[7:0], if ADLJST = 0 (ADC0H[7:2] will be sign-extension of ADC0H.1 for a differential reading, otherwise = 000000b). ADC0H[7:0]:ADC0L[7:6], ...
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ADC0 Programmable Window Detector The ADC0 Programmable Window Detector continuously compares the ADC0 output to user-programmed limits, and notifies the system when an out-of-bound condition is detected. This is especially effective in an interrupt-driven system, saving code space and ...
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C8051F022/3 Figure 6.16. 10-Bit ADC0 Window Interrupt Example: Right Justified Single-Ended Data Input Voltage ADC Data (AD0 - AGND) Word REF x (1023/1024) 0x03FF ADWINT not affected 0x0201 REF x (512/1024) 0x0200 ADC0LTH:ADC0LTL 0x01FF ADWINT=1 0x0101 REF x (256/1024) 0x0100 ...
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Figure 6.17. 10-Bit ADC0 Window Interrupt Example: Right Justified Differential Data Input Voltage ADC Data (AD0 - AD1) Word REF x (511/512) 0x01FF ADWINT not affected 0x0101 REF x (256/512) 0x0100 ADC0LTH:ADC0LTL 0x00FF ADWINT=1 0x0000 REF x (-1/512) 0xFFFF ADC0GTH:ADC0GTL ...
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C8051F022/3 Figure 6.18. 10-Bit ADC0 Window Interrupt Example: Left Justified Single-Ended Data Input Voltage ADC Data (AD0 - AGND) Word REF x (1023/1024) 0xFFC0 ADWINT not affected 0x8040 REF x (512/1024) 0x8000 ADC0LTH:ADC0LTL 0x7FC0 ADWINT=1 0x4040 REF x (256/1024) 0x4000 ...
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Figure 6.19. 10-Bit ADC0 Window Interrupt Example: Left Justified Differential Data Input Voltage ADC Data (AD0 - AD1) Word REF x (511/512) 0x7FC0 ADWINT not affected 0x2040 REF x (128/512) 0x2000 ADC0LTH:ADC0LTL 0x1FC0 ADWINT=1 0x0000 REF x (-1/512) 0xFFC0 ADC0GTH:ADC0GTL ...
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C8051F022/3 Table 6.1. 10-Bit ADC0 Electrical Characteristics (C8051F022/3) VDD = 3.0V, AV+ = 3.0V, VREF = 2.40V (REFBE=0), PGA Gain = 1, -40°C to +85°C unless otherwise specified PARAMETER DC ACCURACY Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Full Scale ...
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ADC1 (8-BIT ADC) The ADC1 subsystem for the C8051F020/1/2/3 consists of an 8-channel, configurable analog multiplexer (AMUX1), a programmable gain amplifier (PGA1), and a 500 ksps, 8-bit successive-approximation-register ADC with inte- grated track-and-hold (see block diagram in Figure 7.1). ...
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C8051F020/1/2/3 7.2. ADC1 Modes of Operation ADC1 has a maximum conversion speed of 500 ksps. The ADC1 conversion clock (SAR1 clock divided version of the system clock, determined by the AD1SC bits in the ADC1CF register (system clock ...
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Figure 7.2. ADC1 Track and Conversion Example Timing A. ADC Timing for External Trigger Source CNVSTR (AD1CM[2:0]=010) SAR1 Clocks Low Power AD1TM=1 or Convert AD1TM=0 Track or Convert B. ADC Timing for Internal Trigger Source Write '1' to AD1BUSY, Timer ...
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C8051F020/1/2/3 7.2.3. Settling Time Requirements When the ADC1 input configuration is changed (i.e., a different MUX or PGA selection), a minimum settling (or tracking) time is required before an accurate conversion can be performed. This settling time is determined by ...
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Figure 7.4. ADC1CF: ADC1 Configuration Register (C8051F020/1/2/3) R/W R/W R/W AD1SC4 AD1SC3 AD1SC2 Bit7 Bit6 Bit5 Bits7-3: AD1SC4-0: ADC1 SAR Conversion Clock Period Bits SAR Conversion clock is derived from system clock by the following equation, where AD1SC refers to ...
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C8051F020/1/2/3 Figure 7.6. ADC1CN: ADC1 Control Register (C8051F020/1/2/3) R/W R/W R/W AD1EN AD1TM AD1INT AD1BUSY AD1CM2 AD1CM1 Bit7 Bit6 Bit5 Bit7: AD1EN: ADC1 Enable Bit. 0: ADC1 Disabled. ADC1 is in low-power shutdown. 1: ADC1 Enabled. ADC1 is active and ...
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Figure 7.7. ADC1: ADC1 Data Word Register R/W R/W R/W Bit7 Bit6 Bit5 Bits7-0: ADC1 Data Word. Figure 7.8. ADC1 Data Word Example 8-bit ADC Data Word appears in the ADC1 Data Word Register as follows: Example: ADC1 Data Word ...
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C8051F020/1/2/3 Table 7.1. ADC1 Electrical Characteristics VDD = 3.0 V, AV+ = 3.0 V, VREF1 = 2.40 V (REFBE=0), PGA1 = 1, -40°C to +85°C unless otherwise specified PARAMETER DC ACCURACY Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Full Scale ...
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DACS, 12-BIT VOLTAGE MODE Each C8051F020/1/2/3 device includes two on-chip 12-bit voltage-mode Digital-to-Analog Converters (DACs). Each DAC has an output swing (VREF-1LSB) for a corresponding input code range of 0x000 to 0xFFF. The DACs may be ...
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C8051F020/1/2/3 8.1.1. Update Output On-Demand In its default mode (DAC0CN.[4:3] = ‘00’) the DAC0 output is updated “on-demand” write to the high-byte of the DAC0 data register (DAC0H). It’s important to note that writes to DAC0L are held, ...
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Figure 8.2. DAC0H: DAC0 High Byte Register R/W R/W R/W Bit7 Bit6 Bit5 Bits7-0: DAC0 Data Word Most Significant Byte. Figure 8.3. DAC0L: DAC0 Low Byte Register R/W R/W R/W Bit7 Bit6 Bit5 Bits7-0: DAC0 Data Word Least Significant Byte. ...
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C8051F020/1/2/3 Figure 8.4. DAC0CN: DAC0 Control Register R/W R/W R/W DAC0EN - - Bit7 Bit6 Bit5 Bit7: DAC0EN: DAC0 Enable Bit. 0: DAC0 Disabled. DAC0 Output pin is disabled; DAC0 is in low-power shutdown mode. 1: DAC0 Enabled. DAC0 Output ...
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Figure 8.5. DAC1H: DAC1 High Byte Register R/W R/W R/W Bit7 Bit6 Bit5 Bits7-0: DAC1 Data Word Most Significant Byte. Figure 8.6. DAC1L: DAC1 Low Byte Register R/W R/W R/W Bit7 Bit6 Bit5 Bits7-0: DAC1 Data Word Least Significant Byte. ...
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C8051F020/1/2/3 Figure 8.7. DAC1CN: DAC1 Control Register R/W R/W R/W DAC1EN - - Bit7 Bit6 Bit5 Bit7: DAC1EN: DAC1 Enable Bit. 0: DAC1 Disabled. DAC1 Output pin is disabled; DAC1 is in low-power shutdown mode. 1: DAC1 Enabled. DAC1 Output ...
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Table 8.1. DAC Electrical Characteristics VDD = 3.0 V, AV+ = 3.0 V, VREF = 2.40 V (REFBE = 0), No Output Load unless otherwise specified PARAMETER STATIC PERFORMANCE Resolution Integral Nonlinearity Differential Nonlinearity Output Noise No Output Filter 100 ...
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C8051F020/1/2/3 90 Notes Rev. 1.4 ...
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VOLTAGE REFERENCE (C8051F020/2) The voltage reference circuit offers full flexibility in operating the ADC and DAC modules. Three voltage reference input pins allow each ADC and the two DACs to reference an external voltage reference or the on-chip voltage ...
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C8051F020/1/2/3 The temperature sensor connects to the highest order input of the ADC0 input multiplexer (see Multiplexer and PGA” on page 43 for C8051F020/1 devices, or page 59 for C8051F022/3 devices). The TEMPE bit within REF0CN enables and disables the ...
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VOLTAGE REFERENCE (C8051F021/3) The internal voltage reference circuit consists ppm/°C (typical) bandgap voltage reference generator and a gain-of-two output buffer amplifier. The internal reference may be routed via the VREF pin to external system ...
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C8051F020/1/2/3 The temperature sensor connects to the highest order input of the ADC0 input multiplexer (see Multiplexer and PGA” on page 43 for C8051F020/1 devices, or page 59 for C8051F022/3 devices). The TEMPE bit within REF0CN enables and disables the ...
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COMPARATORS Each MCU includes two on-board voltage comparators as shown in Figure 11.1. The inputs of each Comparator are available at the package pins. The output of each comparator is optionally available at the package pins via the I/O ...
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C8051F020/1/2/3 Figure 11.2. Comparator Hysteresis Plot CP0+ VIN+ + CP0 CP0- _ VIN- CIRCUIT CONFIGURATION Positive Hysteresis Voltage (Programmed with CP0HYP Bits) VIN- INPUTS VIN OUTPUT V OL Positive Hysteresis Disabled to logic 0. Comparator0 can also be ...
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Figure 11.3. CPT0CN: Comparator0 Control Register R/W R/W R/W CP0EN CP0OUT CP0RIF Bit7 Bit6 Bit5 Bit7: CP0EN: Comparator0 Enable Bit. 0: Comparator0 Disabled. 1: Comparator0 Enabled. Bit6: CP0OUT: Comparator0 Output State Flag. 0: Voltage on CP0+ < CP0-. 1: Voltage ...
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C8051F020/1/2/3 Figure 11.4. CPT1CN: Comparator1 Control Register R/W R/W R/W CP1EN CP1OUT CP1RIF Bit7 Bit6 Bit5 Bit7: CP1EN: Comparator1 Enable Bit. 0: Comparator1 Disabled. 1: Comparator1 Enabled. Bit6: CP1OUT: Comparator1 Output State Flag. 0: Voltage on CP1+ < CP1-. 1: ...
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Table 11.1. Comparator Electrical Characteristics VDD = 3.0 V, AV+ = 3.0 V, -40°C to +85°C unless otherwise specified PARAMETER Response Time 1 CP+ - CP- = 100 mV Response Time 2 CP Common-Mode Rejection ...
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C8051F020/1/2/3 100 Notes Rev. 1.4 ...
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CIP-51 MICROCONTROLLER The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop software. The MCU family has a superset of ...
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C8051F020/1/2/3 Performance The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the standard 8051 architecture standard 8051, all instructions except for MUL and DIV take system clock cycles to exe- cute, ...
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MEMORY” on page 139). The External Memory Interface provides a fast access to off-chip XRAM (or memory- mapped peripherals) via the MOVX instruction. Refer to FACE AND ON-CHIP XRAM” on page 145 Table 12.1. CIP-51 Instruction Set Summary Mnemonic Description ...
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C8051F020/1/2/3 Table 12.1. CIP-51 Instruction Set Summary Mnemonic Description XRL A, #data Exclusive-OR immediate to A XRL direct, A Exclusive- direct byte XRL direct, #data Exclusive-OR immediate to direct byte CLR A Clear A CPL A Complement A ...
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Table 12.1. CIP-51 Instruction Set Summary Mnemonic Description CPL bit Complement direct bit ANL C, bit AND direct bit to Carry ANL C, /bit AND complement of direct bit to Carry ORL C, bit OR direct bit to carry ORL ...
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C8051F020/1/2/3 Notes on Registers, Operands and Addressing Modes Register R0-R7 of the currently selected register bank. @Ri - Data RAM location addressed indirectly through R0 or R1. rel - 8-bit, signed (two’s complement) offset relative to the first ...
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Memory Organization The memory organization of the CIP-51 System Controller is similar to that of a standard 8051. There are two sepa- rate memory spaces: program memory and data memory. Program and data memory share the same address space ...
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C8051F020/1/2/3 12.2.2. Data Memory The CIP-51 implements 256 bytes of internal RAM mapped into the data memory space from 0x00 through 0xFF. The lower 128 bytes of data memory are used for general purpose registers and scratch pad memory. Either ...
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Special Function Registers The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers (SFRs). The SFRs provide control and data exchange with the CIP-51's resources and peripherals. The CIP-51 duplicates the SFRs found in a ...
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C8051F020/1/2/3 Table 12.3. Special Function Registers SFRs are listed in alphabetical order. All undefined SFR locations are reserved. Register Address Description ADC0LTH 0xC7 ADC0 Less-Than High ADC0LTL 0xC6 ADC0 Less-Than Low ADC1CF 0xAB ADC1 Analog Multiplexer Configuration ADC1CN 0xAA ADC1 ...
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Table 12.3. Special Function Registers SFRs are listed in alphabetical order. All undefined SFR locations are reserved. Register Address Description †P6 0x86 Port 6 Latch †P7 0x96 Port 7 Latch †P74OUT 0xB5 Port 4 through 7 Output Mode PCA0CN 0xD8 ...
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C8051F020/1/2/3 Table 12.3. Special Function Registers SFRs are listed in alphabetical order. All undefined SFR locations are reserved. Register Address Description SPI0CFG 0x9A SPI Configuration SPI0CKR 0x9D SPI Clock Rate Control SPI0CN 0xF8 SPI Control SPI0DAT 0x9B SPI Data T2CON ...
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Register Descriptions Following are descriptions of SFRs related to the operation of the CIP-51 System Controller. Reserved bits should not be set to logic l. Future product versions may use these bits to implement new features in which case ...
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C8051F020/1/2/3 Figure 12.6. PSW: Program Status Word R/W R/W R Bit7 Bit6 Bit5 Bit7: CY: Carry Flag. This bit is set when the last arithmetic operation resulted in a carry (addition borrow (subtrac- tion). It ...
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Figure 12.7. ACC: Accumulator R/W R/W R/W ACC.7 ACC.6 ACC.5 Bit7 Bit6 Bit5 Bits7-0: ACC: Accumulator. This register is the accumulator for arithmetic operations. R/W R/W R/W B.7 B.6 B.5 Bit7 Bit6 Bit5 Bits7- Register. This register serves ...
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C8051F020/1/2/3 12.3. Interrupt Handler The CIP-51 includes an extended interrupt system supporting a total of 22 interrupt sources with two priority levels. The allocation of interrupt sources between on-chip peripherals and external inputs pins varies according to the spe- cific ...
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Table 12.4. Interrupt Summary Interrupt Interrupt Source Vector Reset 0x0000 External Interrupt 0 (/INT0) 0x0003 Timer 0 Overflow 0x000B External Interrupt 1 (/INT1) 0x0013 Timer 1 Overflow 0x001B UART0 0x0023 Timer 2 Overflow (or EXF2) 0x002B Serial Peripheral Interface 0x0033 ...
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C8051F020/1/2/3 12.3.3. Interrupt Priorities Each interrupt source can be individually programmed to one of two priority levels: low or high. A low priority inter- rupt service routine can be preempted by a high priority interrupt. A high priority interrupt cannot ...
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Interrupt Register Descriptions The SFRs used to enable the interrupt sources and set their priority level are described below. Refer to the datasheet section associated with a particular on-chip peripheral for information regarding valid interrupt conditions for the peripheral ...
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C8051F020/1/2/3 Figure 12.10. IP: Interrupt Priority R/W R/W R PT2 Bit7 Bit6 Bit5 Bits7-6: UNUSED. Read = 11b, Write = don't care. Bit5: PT2: Timer 2 Interrupt Priority Control. This bit sets the priority of the Timer 2 ...
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Figure 12.11. EIE1: Extended Interrupt Enable 1 R/W R/W R/W ECP1R ECP1F ECP0R Bit7 Bit6 Bit5 Bit7: ECP1R: Enable Comparator1 (CP1) Rising Edge Interrupt. This bit sets the masking of the CP1 interrupt. 0: Disable CP1 Rising Edge interrupt. 1: ...
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C8051F020/1/2/3 Figure 12.12. EIE2: Extended Interrupt Enable 2 R/W R/W R/W EXVLD ES1 EX7 Bit7 Bit6 Bit5 Bit7: EXVLD: Enable External Clock Source Valid (XTLVLD) Interrupt. This bit sets the masking of the XTLVLD interrupt. 0: Disable XTLVLD interrupt. 1: ...
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Figure 12.13. EIP1: Extended Interrupt Priority 1 R/W R/W R/W PCP1R PCP1F PCP0R Bit7 Bit6 Bit5 Bit7: PCP1R: Comparator1 (CP1) Rising Interrupt Priority Control. This bit sets the priority of the CP1 interrupt. 0: CP1 rising interrupt set to low ...
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C8051F020/1/2/3 Figure 12.14. EIP2: Extended Interrupt Priority 2 R/W R/W R/W PXVLD EP1 PX7 Bit7 Bit6 Bit5 Bit7: PXVLD: External Clock Source Valid (XTLVLD) Interrupt Priority Control. This bit sets the priority of the XTLVLD interrupt. 0: XTLVLD interrupt set ...
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Power Management Modes The CIP-51 core has two software programmable power management modes: Idle and Stop. Idle mode halts the CPU while leaving the external peripherals and internal clocks active. In Stop mode, the CPU is halted, all interrupts ...
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C8051F020/1/2/3 Figure 12.15. PCON: Power Control R/W R/W R/W SMOD0 SSTAT0 Reserved Bit7 Bit6 Bit5 Bit7: SMOD0: UART0 Baud Rate Doubler Enable. This bit enables/disables the divide-by-two function of the UART0 baud rate logic for configurations described in the UART0 ...
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RESET SOURCES Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this reset state, the following occur: • CIP-51 halts program execution • Special Function Registers (SFRs) are initialized to their ...
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C8051F020/1/2/3 13.1. Power-on Reset The C8051F020/1/2/3 family incorporates a power supply monitor that holds the MCU in the reset state until VDD rises above the V level during power-up. See Figure 13.2 for timing diagram, and refer to Table 13.1 ...
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External Reset The external /RST pin provides a means for external circuitry to force the MCU into a reset state. Asserting the /RST pin low will cause the MCU to enter the reset state. It may be desirable to ...
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C8051F020/1/2/3 13.8.1. Enable/Reset WDT The watchdog timer is both enabled and reset by writing 0xA5 to the WDTCN register. The user's application soft- ware should include periodic writes of 0xA5 to WDTCN as needed to prevent a watchdog timer overflow. ...
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Figure 13.3. WDTCN: Watchdog Timer Control Register R/W R/W R/W Bit7 Bit6 Bit5 Bits7-0: WDT Control Writing 0xA5 both enables and reloads the WDT. Writing 0xDE followed within 4 system clocks by 0xAD disables the WDT. Writing 0xFF locks out ...
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C8051F020/1/2/3 Figure 13.4. RSTSRC: Reset Source Register R R/W R/W - CNVRSEF C0RSEF Bit7 Bit6 Bit5 (Note: Do not use read-modify-write operations on this register.) Bit7: Reserved. Bit6: CNVRSEF: Convert Start Reset Source Enable and Flag Write: 0: CNVSTR is ...
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Table 13.1. Reset Electrical Characteristics -40°C to +85°C unless otherwise specified. PARAMETER /RST Output High Voltage I /RST Output Low Voltage OL /RST Input High Voltage /RST Input Low Voltage /RST Input Leakage Current VDD for /RST Output Valid AV+ ...
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C8051F020/1/2/3 134 Notes Rev. 1.4 ...
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OSCILLATORS Each MCU includes an internal oscillator and an external oscillator drive circuit, either of which can generate the sys- tem clock. The MCUs operate from the internal oscillator after any reset. This internal oscillator can be enabled/dis- abled ...
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C8051F020/1/2/3 Figure 14.2. OSCICN: Internal Oscillator Control Register R/W R/W R/W MSCLKE - - Bit7 Bit6 Bit5 Bit7: MSCLKE: Missing Clock Enable Bit 0: Missing Clock Detector Disabled 1: Missing Clock Detector Enabled; reset triggered if clock is missing for ...
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Figure 14.3. OSCXCN: External Oscillator Control Register R/W R/W R/W XTLVLD XOSCMD2 XOSCMD1 XOSCMD0 Bit7 Bit6 Bit5 Bit7: XTLVLD: Crystal Oscillator Valid Flag (Valid only when XOSCMD = 11x.) 0: Crystal Oscillator is unused or not yet stable 1: Crystal ...
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C8051F020/1/2/3 14.1. External Crystal Example If a crystal or ceramic resonator is used as an external oscillator source for the MCU, the circuit should be as shown in Figure 14.1, Option 1. The External Oscillator Frequency Control value (XFCN) should ...
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FLASH MEMORY The C8051F020/1/2/3 family includes 64k + 128 bytes of on-chip, reprogrammable FLASH memory for program code and non-volatile data storage. The FLASH memory can be programmed in-system, a single byte at a time, through the JTAG interface ...
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C8051F020/1/2/3 Write/Erase timing is automatically controlled by hardware. Note that code execution in the 8051 is stalled while the FLASH is being programmed or erased. Interrupts that are posted during a FLASH write or erase operation are held pending until ...
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Figure 15.1. FLASH Program Memory Map and Security Bytes Read and Write/Erase Security Bits. (Bit 7 is MSB.) Bit Memory Block 7 0xE000 - 0xFDFD 6 0xC000 - 0xDFFF 5 0xA000 - 0xBFFF 4 0x8000 - 0x9FFF 3 0x6000 - ...
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C8051F020/1/2/3 MCU with proprietary value-added firmware before distribution. The value-added firmware can be protected while allowing additional code to be programmed in remaining program memory space later. The Software Read Limit (SRL 16-bit address that establishes two logical ...
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Figure 15.3. FLSCL: FLASH Memory Control R/W R/W R/W FOSE FRAE Reserved Bit7 Bit6 Bit5 Bit7: FOSE: FLASH One-Shot Timer Enable This is the timer that turns off the sense amps after a FLASH read. 0: FLASH One-Shot Timer disabled. ...
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C8051F020/1/2/3 Figure 15.4. PSCTL: Program Store Read/Write Control R/W R/W R Bit7 Bit6 Bit5 Bits7-3: UNUSED. Read = 00000b, Write = don't care. Bit2: SFLE: Scratchpad FLASH Memory Access Enable. When this bit is set, FLASH reads ...
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EXTERNAL DATA MEMORY INTERFACE AND ON-CHIP XRAM The C8051F020/1/2/3 MCUs include 4k bytes of on-chip RAM mapped into the external data memory space (XRAM), as well as an External Data Memory Interface which can be used to access off-chip ...
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C8051F020/1/2/3 16.2. Configuring the External Memory Interface Configuring the External Memory Interface consists of four steps: 1. Select EMIF on Low Ports (P3, P2, P1, and P0) or High Ports (P7, P6, P5, and P4). 2. Select Multiplexed mode or ...
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Figure 16.1. EMI0CN: External Memory Interface Control R/W R/W R/W PGSEL7 PGSEL6 PGSEL5 Bit7 Bit6 Bit5 Bits7-0: PGSEL[7:0]: XRAM Page Select Bits. The XRAM Page Select Bits provide the high byte of the 16-bit external data memory address when using ...
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C8051F020/1/2/3 16.4. Multiplexed and Non-multiplexed Selection The External Memory Interface is capable of acting in a Multiplexed mode or a Non-multiplexed mode, depending on the state of the EMD2 (EMI0CF.4) bit. 16.4.1. Multiplexed Configuration In Multiplexed mode, the Data Bus ...
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Non-multiplexed Configuration In Non-multiplexed mode, the Data Bus and the Address Bus pins are not shared. An example of a Non-multiplexed Configuration is shown in Figure 16.4. See mation about Non-multiplexed operation. Figure 16.4. Non-multiplexed Configuration Example A[15:0] E ...
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C8051F020/1/2/3 16.5. Memory Mode Selection The external data memory space can be configured in one of four modes, shown in Figure 16.5, based on the EMIF Mode bits in the EMI0CF register (Figure 16.2). These modes are summarized below. More ...
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Split Mode with Bank Select When EMI0CF.[3:2] are set to ‘10’, the XRAM memory map is split into two areas, on-chip space and off-chip space. • Effective addresses below the 4k boundary will access on-chip XRAM space. • Effective ...
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C8051F020/1/2/3 . Figure 16.6. EMI0TC: External Memory Timing Control R/W R/W R/W EAS1 EAS0 EWR3 Bit7 Bit6 Bit5 Bits7-6: EAS1-0: EMIF Address Setup Time Bits. 00: Address setup time = 0 SYSCLK cycles. 01: Address setup time = 1 SYSCLK ...
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Non-multiplexed Mode 16.6.1.1. 16-bit MOVX: EMI0CF[4:2] = ‘101’, ‘110’, or ‘111’. Figure 16.7. Non-multiplexed 16-bit MOVX Timing ADDR[15:8] P1/P5 ADDR[7:0] P2/P6 DATA[7:0] P3/P7 /WR P0.7/P4.7 /RD P0.6/P4.6 ADDR[15:8] P1/P5 ADDR[7:0] P2/P6 DATA[7:0] P3/P7 /RD P0.6/P4.6 /WR P0.7/P4.7 Nonmuxed 16-bit ...
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C8051F020/1/2/3 16.6.1.2. 8-bit MOVX without Bank Select: EMI0CF[4:2] = ‘101’ or ‘111’. Figure 16.8. Non-multiplexed 8-bit MOVX without Bank Select Timing ADDR[15:8] ADDR[7:0] P2/P6 DATA[7:0] P3/P7 /WR P0.7/P4.7 /RD P0.6/P4.6 ADDR[15:8] ADDR[7:0] P2/P6 DATA[7:0] P3/P7 /RD P0.6/P4.6 /WR P0.7/P4.7 154 ...
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MOVX with Bank Select: EMI0CF[4:2] = ‘110’. Figure 16.9. Non-multiplexed 8-bit MOVX with Bank Select Timing ADDR[15:8] P1/P5 ADDR[7:0] P2/P6 DATA[7:0] P3/P7 /WR P0.7/P4.7 /RD P0.6/P4.6 ADDR[15:8] P1/P5 ADDR[7:0] P2/P6 DATA[7:0] P3/P7 /RD P0.6/P4.6 /WR P0.7/P4.7 Nonmuxed 8-bit ...
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C8051F020/1/2/3 16.6.2. Multiplexed Mode 16.6.2.1. 16-bit MOVX: EMI0CF[4:2] = ‘001’, ‘010’, or ‘011’. Figure 16.10. Multiplexed 16-bit MOVX Timing ADDR[15:8] P2/P6 EMIF ADDRESS (8 LSBs) from AD[7:0] P3/P7 T ALEH ALE P0.5/P4.5 /WR P0.7/P4.7 /RD P0.6/P4.6 ADDR[15:8] P2/P6 EMIF ADDRESS ...
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MOVX without Bank Select: EMI0CF[4:2] = ‘001’ or ‘011’. Figure 16.11. Multiplexed 8-bit MOVX without Bank Select Timing ADDR[15:8] EMIF ADDRESS (8 LSBs) from AD[7:0] P3/ ALEH ALE P0.5/P4.5 /WR P0.7/P4.7 /RD P0.6/P4.6 ADDR[15:8] ...
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C8051F020/1/2/3 16.6.2.3. 8-bit MOVX with Bank Select: EMI0CF[4:2] = ‘010’. Figure 16.12. Multiplexed 8-bit MOVX with Bank Select Timing ADDR[15:8] P2/P6 EMIF ADDRESS (8 LSBs) from AD[7:0] P3/ ALEH ALE P0.5/P4.5 /WR P0.7/P4.7 /RD P0.6/P4.6 ADDR[15:8] ...
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Table 16.1. AC Parameters for External Memory Interface PARAMETER DESCRIPTION T System Clock Period SYSCLK T Address / Control Setup Time ACS T Address / Control Pulse Width ACW T Address / Control Hold Time ACH T Address Latch Enable ...
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C8051F020/1/2/3 160 Notes Rev. 1.4 ...
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PORT INPUT/OUTPUT The C8051F020/1/2/3 are fully integrated mixed-signal System on a Chip MCUs with 64 digital I/O pins (C8051F020/ digital I/O pins (C8051F021/3), organized as 8-bit Ports. The lower ports: P0, P1, P2, and P3, are both ...
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C8051F020/1/2/3 The C8051F020/1/2/3 devices have a wide array of digital resources which are available through the four lower I/O Ports: P0, P1, P2, and P3. Each of the pins on P0, P1, P2, and P3, can be defined as a ...
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Ports 0 through 3 and the Priority Crossbar Decoder The Priority Crossbar Decoder, or “Crossbar”, allocates and assigns Port pins on Port 0 through Port 3 to the digital peripherals (UARTs, SMBus, PCA, Timers, etc.) on the device using ...
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C8051F020/1/2 Port pin without assigning RX0 as well. Each combination of enabled peripherals results in a unique device pin- out. All Port pins on Ports 0 through 3 that are not allocated by the Crossbar can be accessed ...
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Configuring Port Pins as Digital Inputs A Port pin is configured as a digital input by setting its output mode to “Open-Drain” and writing a logic 1 to the associated bit in the Port Data register. For example, P3.7 ...
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C8051F020/1/2/3 17.1.7. External Memory Interface Pin Assignments If the External Memory Interface (EMIF) is enabled on the Low ports (Ports 0 through 3), EMIFLE (XBR2.1) should be set to a logic 1 so that the Crossbar will not assign peripherals ...
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Figure 17.5. Priority Crossbar Decode Table (EMIFLE = 1; EMIF in Non-multiplexed Mode; P1MDIN = 0xFF) P0 PIN I TX0 RX0 SCK MISO ...
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C8051F020/1/2/3 17.1.8. Crossbar Pin Assignment Example In this example (Figure 17.6), we configure the Crossbar to allocate Port pins for UART0, the SMBus, UART1, /INT0, and /INT1 (8 pins total). Additionally, we configure the External Memory Interface to operate in ...
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Figure 17.6. Crossbar Example: (EMIFLE = 1; EMIF in Multiplexed Mode; P1MDIN = 0xE3; XBR0 = 0x05; XBR1 = 0x14; XBR2 = 0x46) P0 PIN I TX0 ...
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C8051F020/1/2/3 Figure 17.7. XBR0: Port I/O Crossbar Register 0 R/W R/W R/W CP0E ECI0E Bit7 Bit6 Bit5 Bit7: CP0E: Comparator 0 Output Enable Bit. 0: CP0 unavailable at Port pin. 1: CP0 routed to Port pin. Bit6: ECI0E: PCA0 External ...
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Figure 17.8. XBR1: Port I/O Crossbar Register 1 R/W R/W R/W SYSCKE T2EXE T2E Bit7 Bit6 Bit5 Bit7: SYSCKE: /SYSCLK Output Enable Bit. 0: /SYSCLK unavailable at Port pin. 1: /SYSCLK routed to Port pin. Bit6: T2EXE: T2EX Input Enable ...
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C8051F020/1/2/3 Figure 17.9. XBR2: Port I/O Crossbar Register 2 R/W R/W R/W WEAKPUD XBARE - Bit7 Bit6 Bit5 Bit7: WEAKPUD: Weak Pull-Up Disable Bit. 0: Weak pull-ups globally enabled. 1: Weak pull-ups globally disabled. Bit6: XBARE: Crossbar Enable Bit. 0: ...
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Figure 17.10. P0: Port0 Data Register R/W R/W R/W P0.7 P0.6 P0.5 Bit7 Bit6 Bit5 Bits7-0: P0.[7:0]: Port0 Output Latch Bits. (Write - Output appears on I/O pins per XBR0, XBR1, XBR2, and XBR3 Registers) 0: Logic Low Output. 1: ...
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C8051F020/1/2/3 Figure 17.12. P1: Port1 Data Register R/W R/W R/W P1.7 P1.6 P1.5 Bit7 Bit6 Bit5 Bits7-0: P1.[7:0]: Port1 Output Latch Bits. (Write - Output appears on I/O pins per XBR0, XBR1, XBR2, and XBR3 Registers) 0: Logic Low Output. ...
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Figure 17.14. P1MDOUT: Port1 Output Mode Register R/W R/W R/W Bit7 Bit6 Bit5 Bits7-0: P1MDOUT.[7:0]: Port1 Output Mode Bits. 0: Port Pin output mode is configured as Open-Drain. 1: Port Pin output mode is configured as Push-Pull. Note: SDA, SCL, ...
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C8051F020/1/2/3 Figure 17.17. P3: Port3 Data Register R/W R/W R/W P3.7 P3.6 P3.5 Bit7 Bit6 Bit5 Bits7-0: P3.[7:0]: Port3 Output Latch Bits. (Write - Output appears on I/O pins per XBR0, XBR1, XBR2, and XBR3 Registers) 0: Logic Low Output. ...
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Figure 17.19. P3IF: Port3 Interrupt Flag Register R/W R/W R IE7 IE6 - Bit7 Bit6 Bit5 Bit7: IE7: External Interrupt 7 Pending Flag 0: No falling edge has been detected on P3.7 since this bit was last cleared. 1: This ...
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C8051F020/1/2/3 Port Data register will cause the Port pin to be driven to GND, and a logic 1 will cause the Port pin to assume a high- impedance state. The Open-Drain configuration is useful to prevent contention between devices in ...
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Figure 17.20. P74OUT: Ports Output Mode Register R/W R/W R/W P7H P7L P6H Bit7 Bit6 Bit5 Bit7: P7H: Port7 Output Mode High Nibble Bit. 0: P7.[7:4] configured as Open-Drain. 1: P7.[7:4] configured as Push-Pull. Bit6: P7L: Port7 ...
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C8051F020/1/2/3 Figure 17.21. P4: Port4 Data Register R/W R/W R/W P4.7 P4.6 P4.5 Bit7 Bit6 Bit5 Bits7-0: P4.[7:0]: Port4 Output Latch Bits. Write - Output appears on I/O pins. 0: Logic Low Output. 1: Logic High Output (Open-Drain if corresponding ...
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Figure 17.23. P6: Port6 Data Register R/W R/W R/W P6.7 P6.6 P6.5 Bit7 Bit6 Bit5 Bits7-0: P6.[7:0]: Port6 Output Latch Bits. Write - Output appears on I/O pins. 0: Logic Low Output. 1: Logic High Output (Open-Drain if corresponding P74OUT ...
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C8051F020/1/2/3 182 Notes Rev. 1.4 ...
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SYSTEM MANAGEMENT BUS / I The SMBus0 I/O interface is a two-wire, bi-directional serial bus. SMBus0 is compliant with the System Manage- ment Bus Specification, version 1.1, and compatible with the I system controller are byte oriented with the ...
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C8051F020/1/2/3 Figure 18.2 shows a typical SMBus configuration. The SMBus0 interface will work at any voltage between 3.0 V and 5.0 V and different devices on the bus may operate at different voltage levels. The bi-directional SCL (serial clock) and ...
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SMBus Protocol Two types of data transfers are possible: data transfers from a master transmitter to an addressed slave receiver (WRITE), and data transfers from an addressed slave transmitter to a master receiver (READ). The master device ini- tiates ...
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C8051F020/1/2/3 18.2.3. SCL Low Timeout If the SCL line is held low by a slave device on the bus, no further communication is possible. Furthermore, the mas- ter cannot force the SCL line high to correct the error condition. To ...
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SMBus Transfer Modes The SMBus0 interface may be configured to operate as a master and/or a slave. At any particular time, the interface will be operating in one of the following modes: Master Transmitter, Master Receiver, Slave Transmitter, or ...
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C8051F020/1/2/3 18.3.3. Slave Transmitter Mode Serial data is transmitted on SDA while the serial clock is received on SCL. The SMBus0 interface receives a START followed by data byte containing the slave address and direction bit. If the received slave ...
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SMBus Special Function Registers The SMBus0 serial interface is accessed and controlled through five SFRs: SMB0CN Control Register, SMB0CR Clock Rate Register, SMB0ADR Address Register, SMB0DAT Data Register and SMB0STA Status Register. The five special function registers related to ...
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C8051F020/1/2/3 Setting the SMBus0 Free Timer Enable bit (FTE, SMB0CN.1) to logic 1 enables the timer in SMB0CR. When SCL goes high, the timer in SMB0CR counts up. A timer overflow indicates a free bus timeout: if SMBus0 is waiting ...
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Figure 18.8. SMB0CN: SMBus0 Control Register R R/W R/W BUSY ENSMB STA Bit7 Bit6 Bit5 Bit7: BUSY: Busy Status Flag. 0: SMBus0 is free 1: SMBus0 is busy Bit6: ENSMB: SMBus Enable. This bit enables/disables the SMBus serial interface. 0: ...
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C8051F020/1/2/3 18.4.2. Clock Rate Register Figure 18.9. SMB0CR: SMBus0 Clock Rate Register R/W R/W R/W Bit7 Bit6 Bit5 Bits7-0: SMB0CR.[7:0]: SMBus0 Clock Rate Preset The SMB0CR Clock Rate register controls the frequency of the serial clock SCL in master mode. ...
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Data Register The SMBus0 Data register SMB0DAT holds a byte of serial data to be transmitted or one that has just been received. Software can read or write to this register while the SI flag is set to logic ...
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C8051F020/1/2/3 18.4.5. Status Register The SMB0STA Status register holds an 8-bit status code indicating the current state of the SMBus0 interface. There are 28 possible SMBus0 states, each with a corresponding unique status code. The five most significant bits of ...
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Table 18.1. SMB0STA Status Codes and States Status Mode SMBus State Code 0x08 START condition transmitted. 0x10 Repeated START condition transmitted. 0x18 Slave Address + W transmitted. ACK received. 0x20 Slave Address + W transmitted. NACK received. 0x28 Data byte ...
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C8051F020/1/2/3 Table 18.1. SMB0STA Status Codes and States Status Mode Code 0x60 Own slave address + W received. ACK trans- mitted. 0x68 Arbitration lost in sending SLA + R/W as mas- ter. Own address + W received. ACK transmit- ted. ...
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SERIAL PERIPHERAL INTERFACE BUS (SPI0) The Serial Peripheral Interface (SPI0) provides access to a four-wire, full-duplex, serial bus. SPI0 may operate as a master or a slave, and supports the connection of multiple slaves and masters on the same ...
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C8051F020/1/2/3 19.1. Signal Descriptions The four signals used by SPI0 (MOSI, MISO, SCK, NSS) are described below. 19.1.1. Master Out, Slave In (MOSI) The master-out, slave-in (MOSI) signal is an output from a master device and an input to slave ...
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SPI0 Operation Only a SPI master device can initiate a data transfer. SPI0 is placed in master mode by setting the Master Enable flag (MSTEN, SPI0CN.1). Writing a byte of data to the SPI0 data register (SPI0DAT) when in ...
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C8051F020/1/2/3 Multiple masters may reside on the same bus. A Mode Fault flag (MODF, SPI0CN.5) is set to logic 1 when SPI0 is configured as a master (MSTEN = 1) and its slave select signal NSS is pulled low. When ...