MCF53281CVM240J Freescale Semiconductor, MCF53281CVM240J Datasheet - Page 36

• Manufacturer Part Number: MCF53281CVM240J
• Description: IC MPU RISC 240MHZ 256MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF532xr

Specifications of MCF53281CVM240J

• Core Processor: Coldfire V3
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, SPI, SSI, UART/USART, USB, USB OTG
• Peripherals: DMA, LCD, PWM, WDT
• Number Of I /o: 94
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Processor Series: MCF532xx
• Core: ColdFire V3
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Electrical Characteristics
Table 22
Figure 22
36
I2C_SDA
I2C_SCL
1
2
3
lists specifications for the I
Num
shows timing for the values in
Output numbers depend on the value programmed into the IFDR; an IFDR programmed with the maximum
frequency (IFDR = 0x20) results in minimum output timings as shown in
designed to scale the actual data transition time to move it to the middle of the SCL low period. The actual
position is affected by the prescale and division values programmed into the IFDR; however, the numbers
given in
Because I2C_SCL and I2C_SDA are open-collector-type outputs, which the processor can only actively drive
low, the time I2C_SCL or I2C_SDA take to reach a high level depends on external signal capacitance and
pull-up resistor values.
Specified at a nominal 50-pF load.
I2
I3
I4
I5
I6
I7
I8
I9
I1
1
1
2
1
3
1
1
1
1
Num
I5
I6
I7
I8
I9
Start condition hold time
Clock low period
I2C_SCL/I2C_SDA rise time (V
Data hold time
I2C_SCL/I2C_SDA fall time (V
Clock high time
Data setup time
Start condition setup time (for repeated start condition only)
Stop condition setup time
Table 21. I
Table 22
I1
I2C_SCL/I2C_SDA fall time (V
Clock high time
Data setup time
Start condition setup time (for repeated start condition only)
Stop condition setup time
Table 22. I
are minimum values.
2
C Input Timing Specifications between SCL and SDA (continued)
I2
MCF532x ColdFire
2
2
C Output Timing Specifications between SCL and SDA
C output timing parameters shown in
Table 22
Characteristic
Figure 22. I
Characteristic
I4
IH
IL
= 2.4 V to V
and
= 0.5 V to V
IH
I6
®
= 2.4 V to V
Table
2
Microprocessor Data Sheet, Rev. 5
C Input/Output Timings
21.
IL
I7
IH
= 0.5 V)
= 2.4 V)
IL
= 0.5 V)
Figure
I8
22.
Table
Min
I5
10
10
20
10
—
—
Min
6
7
2
—
4
0
2
2
22. The I
I3
Max
—
Max
—
—
—
1
—
—
—
—
—
—
—
—
3
2
C interface is
Freescale Semiconductor
Units
t
ms
t
t
ns
cyc
cyc
cyc
Units
I9
t
t
t
t
t
t
t
µs
ns
cyc
cyc
cyc
cyc
cyc
cyc
cyc