M30260F6AGP#U9A Renesas Electronics America, M30260F6AGP#U9A Datasheet - Page 178
![IC M16C/26A MCU FLASH 48K 48LQFP](/photos/12/39/123991/m30260f6agp_u9a_sml.jpg)
M30260F6AGP#U9A
Manufacturer Part Number
M30260F6AGP#U9A
Description
IC M16C/26A MCU FLASH 48K 48LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/Tiny/26r
Specifications of M30260F6AGP#U9A
Core Processor
M16C/60
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IEBus, SIO, UART/USART
Peripherals
DMA, PWM, Voltage Detect, WDT
Number Of I /o
39
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
48-LQFP
For Use With
R0K33026AS000BE - KIT DEV EVALUATION M16C/26A
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Manufacturer
Quantity
Price
Part Number:
M30260F6AGP#U9AM30260F6AGP#D3
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
M30260F6AGP#U9AM30260F6AGP#U3
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
M30260F6AGP#U9AM30260F6AGP#U3A
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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R
M
e
E
1
. v
J
6
Figure 13.1.3.1. I
0
C
2
9
SDA2
0 .
SCL2
B
2 /
NOTE:
0
This diagram applies to the case where the SMD2 to SMD0 bits in the the U2MR register is set to "010
register is set to "1".
IICM
IICM2, SWC, ALS, SWC2, SDHI : Bits in the U2SMR2
STSPSEL, ACKD, ACKC
0
6
2
A
1. If the IICM bit is set to "1", the pin can be read even when the PD7_1 bit is set to "1" (output mode).
0
F
2
e
G
0 -
b
o r
1 .
2
0
, 5
u
0
p
Noise
Filter
2
(
0
M
0
Noise
Filter
7
1
2
6
C bus Mode Block Diagram
C
Delay
circuit
page 159
ACKC=1
ACKD bit
IICM=0
IICM=1
2 /
6
Falling edge
detection
, A
UART2
: Bit in the U2SMR
: Bits in the U2SMR4
STSPSEL=0
M
I/O port
STSPSEL=1
STSPSEL=0
Start condition
detection
Stop condition
detection
ACKC=0
1
f o
6
STSPSEL=1
C
3
2
2 /
D
9
T
6
Q
Q
, B
R
SDHI
M
Arbitration
Port register
(1)
Internal clock
External
clock
1
6
ALS
C
SWC2
2 /
R
S
6
) T
S
R
CLK
control
SDA
SCL
Start and stop condition generation block
Q
Transmission
register
Reception register
9th bit falling edge
STSP
Bus
busy
STSP
UART2
UART2
UART2
SWC
9th bit
D
D
T
T
Q
Q
IICM2=1
ACK
IICM=1 and
IICM2=0
IICM2=1
IICM=1 and
IICM2=0
NACK
2
" and the IICM bit in the U2SMR
Start/stop condition detection
interrupt request
UART2 transmit,
NACK interrupt
request
UART2 receive,
ACK interrupt request,
DMA1 request
DMA0, DMA1 request
DMA0
13. Serial I/O
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