HD64F2317VTEBL25 Renesas Electronics America, HD64F2317VTEBL25 Datasheet
HD64F2317VTEBL25
Specifications of HD64F2317VTEBL25
Related parts for HD64F2317VTEBL25
HD64F2317VTEBL25 Summary of contents
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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...
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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
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The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. H8S/2319 Group 16 Hardware Manual Renesas 16-Bit ...
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This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in ...
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General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If ...
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Rev.7.00 Feb. 14, 2007 page iv of xxxii REJ09B0089-0700 ...
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This LSI is a single-chip microcomputer made up of the H8S/2000 CPU with an internal 32-bit architecture as its core, and the peripheral functions required to configure a system. This LSI is equipped with ROM, RAM, a bus controller, data ...
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In order to understand the details of a register when its name is known The addresses, bits, and initial values of the registers are summarized in appendix B, Internal I/O Registers. Examples: Register name: Bit order: Number notation: Binary ...
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Main Revisions for This Edition Item Page 1.3.1 Pin 13 Arrangement Figure 1.6 HD64F2319CLP, HD6432317SLP, HD6432316SLP Pin Arrangement (TLP- 113V: Top View) 2.6.3 Table of 45 Instructions Classified by Function Table 2.3 Instructions Classified by Function 6.3.5 Chip Select 156 ...
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Item Page 8.4.2 Register 247, 248 Configuration 8.6.2 Register 254 to Configuration 256 8.11.2 Register 284, 285 Configuration 8.12.2 Register 294, 295 Configuration Rev.7.00 Feb. 14, 2007 page viii of xxxii REJ09B0089-0700 Revision (See Manual for Details) Port 3 Data ...
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Item Page 12.2.8 Bit Rate 452 Register (BRR) Table 12.3 BRR Settings for Various Bit Rates (Asynchronous Mode) 14.4.3 Input 545 Sampling and A/D Conversion Time Figure 14.5 A/D Conversion Timing 17.4.1 Features 571 Revision (See Manual for Details) Table ...
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Item Page 17.8.3 Error 604 Protection 17.11.2 Socket 609 Adapters and Memory Map 17.13.1 Features 629 17.17.3 Error 664 Protection 17.20.2 Socket 670 Adapters and Memory Map 17.22.1 Features 686 17.22.4 Mode 690 Comparison Table 17.46 Comparison of Programming Modes ...
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Item Page 17.24.2 User 729 Program Mode 730 17.25 Protection 738 17.29.1 Serial 754 Communication Interface Specification for Boot Mode 759 760 Revision (See Manual for Details) Programming Procedure in User Program Mode: Description amended (g) Initialization • The general ...
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Item Page 17.29.1 Serial 773 Communication Interface Specification for Boot Mode 17.29.3 Procedure 791 Program and storable Area for Programming Data Table 17.73 (3) Usable Area for Programming in User Boot Mode 19.1 Overview 802 Table 19.1 Operating Modes 20.2.5 ...
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Item Page 20.2.6 Flash 848 Memory Characteristics Table 20.19 Flash Memory Characteristics 20.1 Electrical 817 Characteristics of Mask ROM Version (H8S/2319, H8S/2318, H8S/2317S, H8S/2316S, H8S/2315, H8S/2314) and ROMless Version (H8S/2312S) 20.2.6 Flash Memory 849 Characteristics Table 20.19 Flash Memory Characteristics ...
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Item Page 20.3.6 Flash Memory 860 Characteristics Table 20.29 Flash Memory Characteristics Appendix E Products 1103 Lineup Table E.1 H8S/2319 Group Products Lineup 1104 F. Package Dimensions Figure F.4 TLP-113V Package Dimensions All trademarks and registered trademarks are the property ...
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Section 1 Overview............................................................................................1 1.1 Overview........................................................................................................................... 1 1.2 Block Diagram .................................................................................................................. 8 1.3 Pin Description.................................................................................................................. 9 1.3.1 Pin Arrangement .................................................................................................. 9 1.3.2 Pin Functions in Each Operating Mode ............................................................... 14 1.3.3 Pin Functions ....................................................................................................... 18 Section 2 CPU....................................................................................................27 2.1 Overview........................................................................................................................... 27 ...
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Bus-Released State............................................................................................... 66 2.8.6 Power-Down State ............................................................................................... 66 2.9 Basic Timing ..................................................................................................................... 67 2.9.1 Overview.............................................................................................................. 67 2.9.2 On-Chip Memory (ROM, RAM) ......................................................................... 67 2.9.3 On-Chip Supporting Module Access Timing....................................................... 69 2.9.4 External Address Space Access Timing .............................................................. 70 2.10 ...
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Memory Map in Each Operating Mode ............................................................................ 81 Section 4 Exception Handling ...........................................................................99 4.1 Overview........................................................................................................................... 99 4.1.1 Exception Handling Types and Priority............................................................... 99 4.1.2 Exception Handling Operation............................................................................. 100 4.1.3 Exception Vector Table ....................................................................................... 100 4.2 Reset.................................................................................................................................. 102 4.2.1 Overview.............................................................................................................. ...
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Usage Notes ...................................................................................................................... 134 5.5.1 Contention between Interrupt Generation and Disabling..................................... 134 5.5.2 Instructions that Disable Interrupts ...................................................................... 135 5.5.3 Times when Interrupts are Disabled .................................................................... 135 5.5.4 Interrupts during Execution of EEPMOV Instruction.......................................... 135 5.6 DTC Activation by ...
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Pin States in Idle Cycle ........................................................................................ 176 6.7 Bus Release....................................................................................................................... 177 6.7.1 Overview.............................................................................................................. 177 6.7.2 Operation ............................................................................................................. 177 6.7.3 Pin States in External Bus Released State............................................................ 178 6.7.4 Transition Timing ................................................................................................ 179 6.7.5 Usage Note........................................................................................................... 180 6.8 Bus Arbitration.................................................................................................................. ...
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Procedures for Using DTC................................................................................... 210 7.3.12 Examples of Use of the DTC ............................................................................... 211 7.4 Interrupts ........................................................................................................................... 215 7.5 Usage Notes ...................................................................................................................... 215 Section 8 I/O Ports.............................................................................................217 8.1 Overview........................................................................................................................... 217 8.2 Port 1................................................................................................................................. 222 8.2.1 Overview.............................................................................................................. 222 8.2.2 Register ...
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Register Configuration......................................................................................... 272 8.9.3 Pin Functions ....................................................................................................... 275 8.9.4 MOS Input Pull-Up Function............................................................................... 276 8.10 Port E ................................................................................................................................ 277 8.10.1 Overview.............................................................................................................. 277 8.10.2 Register Configuration......................................................................................... 278 8.10.3 Pin Functions ....................................................................................................... 280 8.10.4 MOS Input Pull-Up Function............................................................................... 282 8.11 Port ...
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Synchronous Operation........................................................................................ 349 9.4.4 Buffer Operation .................................................................................................. 351 9.4.5 Cascaded Operation ............................................................................................. 355 9.4.6 PWM Modes ........................................................................................................ 357 9.4.7 Phase Counting Mode .......................................................................................... 363 9.5 Interrupts ........................................................................................................................... 369 9.5.1 Interrupt Sources and Priorities............................................................................ 369 9.5.2 DTC Activation.................................................................................................... 371 9.5.3 ...
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Contention between TCOR Write and Compare Match ...................................... 410 10.6.4 Contention between Compare Matches A and B ................................................. 411 10.6.5 Switching of Internal Clocks and TCNT Operation............................................. 411 10.6.6 Interrupts and Module Stop Mode ....................................................................... 413 Section 11 Watchdog ...
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Serial Mode Register (SMR)................................................................................ 438 12.2.6 Serial Control Register (SCR).............................................................................. 441 12.2.7 Serial Status Register (SSR) ................................................................................ 445 12.2.8 Bit Rate Register (BRR) ...................................................................................... 449 12.2.9 Smart Card Mode Register (SCMR) .................................................................... 457 12.2.10 Module Stop Control Register (MSTPCR) ...
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Pin Configuration................................................................................................. 533 14.1.4 Register Configuration......................................................................................... 534 14.2 Register Descriptions ........................................................................................................ 535 14.2.1 A/D Data Registers (ADDRA to ADDRD) ............................................. 535 14.2.2 A/D Control/Status Register (ADCSR) ............................................................... 536 14.2.3 A/D Control Register (ADCR) ............................................................................ 538 14.2.4 ...
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Register Configuration......................................................................................... 566 17.2 Register Descriptions ........................................................................................................ 566 17.2.1 Mode Control Register (MDCR) ......................................................................... 566 17.2.2 Bus Control Register L (BCRL) .......................................................................... 567 17.3 Operation........................................................................................................................... 567 17.4 Overview of Flash Memory (H8S/2318 F-ZTAT, H8S/2317 F-ZTAT, H8S/2315 F-ZTAT, H8S/2314 F-ZTAT).......................................................................... ...
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Progremmer Mode Setting ................................................................................... 608 17.11.2 Socket Adapters and Memory Map...................................................................... 609 17.11.3 Programmer Mode Operation .............................................................................. 611 17.11.4 Memory Read Mode ............................................................................................ 613 17.11.5 Auto-Program Mode ............................................................................................ 616 17.11.6 Auto-Erase Mode ................................................................................................. 618 17.11.7 Status Read Mode ................................................................................................ ...
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Flash Memory Protection.................................................................................................. 662 17.17.1 Hardware Protection ............................................................................................ 662 17.17.2 Software Protection.............................................................................................. 663 17.17.3 Error Protection.................................................................................................... 664 17.18 Flash Memory Emulation in RAM ................................................................................... 666 17.18.1 Emulation in RAM............................................................................................... 666 17.18.2 RAM Overlap ...................................................................................................... 667 17.19 Interrupt Handling when ...
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Hardware Protection ............................................................................................ 738 17.25.2 Software Protection.............................................................................................. 739 17.25.3 Error Protection.................................................................................................... 739 17.26 Flash Memory Emulation in RAM ................................................................................... 741 17.27 Switching between User MAT and User Boot MAT ........................................................ 744 17.27.1 Usage Notes ......................................................................................................... 745 17.28 PROM Mode..................................................................................................................... ...
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Module Stop Control Register (MSTPCR) .......................................................... 807 19.3 Medium-Speed Mode........................................................................................................ 807 19.4 Sleep Mode ....................................................................................................................... 808 19.5 Module Stop Mode............................................................................................................ 809 19.5.1 Module Stop Mode .............................................................................................. 809 19.5.2 Usage Notes ......................................................................................................... 810 19.6 Software Standby Mode.................................................................................................... 811 19.6.1 Software ...
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Flash Memory Characteristics ............................................................................. 860 20.3.7 Usage Note (Internal voltage step down for the H8S/2319C F-ZTAT) ............... 861 20.4 Usage Note........................................................................................................................ 861 Appendix A Instruction Set ...............................................................................863 A.1 Instruction List .................................................................................................................. 863 A.2 Instruction Codes .............................................................................................................. 887 A.3 Operation ...
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Rev.7.00 Feb. 14, 2007 page xxxii of xxxii REJ09B0089-0700 ...
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Overview The H8S/2319 Group is a series of microcomputer (MCU: microcomputer unit), built around the H8S/2000 CPU, employing Renesas's proprietary architecture, and equipped with supporting functions on-chip. The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen ...
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Section 1 Overview Table 1.1 Overview Item Specification • CPU General-register machine ⎯ Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers) • High-speed operation suitable for realtime control ⎯ Maximum clock rate: 25 MHz ...
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Item Specification • 8-bit timer, 8-bit up-counter (external event count capability) 2 channels • Two time constant registers • Two-channel connection possible • Watchdog timer Watchdog timer or interval timer selectable • Serial Asynchronous mode or synchronous mode selectable communication ...
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Section 1 Overview Item Specification • Power-down state Medium-speed mode • Sleep mode • Module stop mode • Software standby mode • Hardware standby mode • Variable clock division ratio • Operating modes Eight MCU operating modes (H8S/2318 F-ZTAT, H8S/2317 ...
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Item Specification • Operating modes Four MCU operating modes (ROMless, mask ROM versions, H8S/2319 F- ZTAT, and H8S/2319C F-ZTAT) CPU Operating Mode Mode — Advanced On-chip ROM disabled ...
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Section 1 Overview Item Specification Product lineup Operating power supply voltage Operating frequency Model O: Products in the current lineup Note: * The on-chip debug function can be used with the E10A emulator (E10A compatible version). However, some function modules ...
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Item Specification • Other features Differences between H8S/2319 F-ZTAT and H8S/2319C F-ZTAT ⎯ On-chip RAM H8S/2319 F-ZTAT: 8 kbytes (H'FFDC00 to H'FFFBFF) H8S/2319C F-ZTAT: 16 kbytes (H'FFBC00 to H'FFFBFF) ⎯ On-chip flash memory The H8S/2319 F-ZTAT and H8S/2319C F-ZTAT both ...
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Section 1 Overview 1.2 Block Diagram MD2 MD1 MD0 EXTAL XTAL STBY RES ) * 1 WDTOVF (FWE, EMLE NMI PF7/φ PF6/AS PF5/RD PF4/HWR Port PF3/LWR/IRQ3 F PF2/WAIT/IRQ2/DREQO PF1/BACK/IRQ1/CS5 PF0/BREQ/IRQ0/CS4 PG4/CS0 PG3/CS1/CS7 Port PG2/CS2 G PG1/CS3/IRQ7/CS6 PG0/ADTRG/IRQ6 Notes: ...
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Pin Description 1.3.1 Pin Arrangement PF0/BREQ/IRQ0/CS4 ref P40/AN0 79 P41/AN1 80 P42/AN2 81 P43/AN3 82 P44/AN4 83 P45/AN5 84 P46/AN6/DA0 85 P47/AN7/DA1 P24/TIOCA4/TMRI1 89 P25/TIOCB4/TMCI1 90 ...
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Section 1 Overview P40/AN0 81 P41/AN1 82 P42/AN2 83 P43/AN3 84 P44/AN4 85 P45/AN5 86 P46/AN6/DA0 87 P47/AN7/DA1 P24/TIOCA4/TMRI1 91 P25/TIOCB4/TMCI1 92 P26/TIOCA5/TMO0 93 P27/TIOCB5/TMO1 94 PG0/ADTRG/IRQ6 95 PG1/CS3/IRQ7/CS6 96 PG2/CS2 97 PG3/CS1/CS7 ...
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E10A compatible version PF0/BREQ/IRQ0/CS4 ref P40/AN0 79 P41/AN1 80 P42/AN2 81 P43/AN3 82 P44/AN4 83 P45/AN5 84 P46/AN6/DA0 85 P47/AN7/DA1 P24/TIOCA4/TMRI1 89 P25/TIOCB4/TMCI1 90 P26/TIOCA5/TMO0 91 P27/TIOCB5/TMO1 ...
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Section 1 Overview E10A compatible version P40/AN0 81 P41/AN1 82 P42/AN2 83 P43/AN3 84 P44/AN4 85 P45/AN5 86 P46/AN6/DA0 87 P47/AN7/DA1 P24/TIOCA4/TMRI1 91 P25/TIOCB4/TMCI1 92 P26/TIOCA5/TMO0 93 P27/TIOCB5/TMO1 94 PG0/ADTRG/IRQ6 95 PG1/CS3/IRQ7/CS6 96 ...
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NC P11 PG3 PG2 A P10 VCC PG4 P12 B P13 P16 NC P14 C P15 VSS P17 NC D P30 P33 P32 P31 E P34 PE2 PE3 P35 F PE1 PE5 VSS PE0 G PE4 NC ...
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Section 1 Overview 1.3.2 Pin Functions in Each Operating Mode Table 1.2 shows the pin functions in each of the operating modes. Table 1.2 Pin Functions in Each Operating Mode Pin No. TFP-100B, Mode TFP-100G FP-100A TLP-113V ...
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Pin No. TFP-100B, Mode TFP-100G FP-100A TLP-113V D12 D13 D14 D15 ...
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Section 1 Overview Pin No. TFP-100B, Mode TFP-100G FP-100A TLP-113V 4 WDTOVF ⎯ (FWE, EMLE G10 MD2 RES 62 64 F11 NMI STBY E11 V CC ...
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Pin No. TFP-100B, Mode TFP-100G FP-100A TLP-113V P25/TIOCB4/ TMCI1 P26/TIOCA5/ TMO0 P27/TIOCB5/ TMO1 PG0/IRQ6/ ADTRG PG1/CS3/ IRQ7/CS6 PG2/CS2 ...
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Section 1 Overview 1.3.3 Pin Functions Table 1.3 Pin Functions TFP-100B, TFP-100G FP-100A TLP-113V Type Symbol Power V 40, 65, CC supply 18, SS 31, 49, 68 Internal voltage step-down pin ...
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TFP-100B, Type Symbol TFP-100G FP-100A TLP-113V Operating MD2 to 61, 58, mode MD0 57 control Pin No. I/O Name and Function 63, 60, G10, H10, Input Mode pins: These pins set the 59 H9 operating mode. The relation between the ...
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Section 1 Overview TFP-100B, Type Symbol TFP-100G FP-100A TLP-113V Operating MD2 to 61, 58, mode MD0 57 control RES System 62 control STBY 64 BREQ 76 BREQO 74 BACK 75 FWE * 4 60 EMLE * 5 60 Rev.7.00 Feb. ...
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TFP-100B, Type Symbol TFP-100G FP-100A TLP-113V Interrupts NMI 63 IRQ7 to 94, 93, IRQ0 13, 12 Address A23 bus A0 100 Data bus D15 ...
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Section 1 Overview TFP-100B, Type Symbol TFP-100G FP-100A TLP-113V WAIT Bus control 74 16-bit timer- TCLKD pulse unit TCLKA (TPU) TIOCA0, 99, 100, TIOCB0 TIOCC0, TIOCD0 TIOCA1 TIOCB1 TIOCA2 ...
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TFP-100B, Type Symbol TFP-100G FP-100A TLP-113V WDTOVF * 6 Watchdog 60 timer (WDT) Serial com- TxD1 munication TxD0 interface RxD1, 11, 10 (SCI) Smart RxD0 Card SCK1 13, 12 interface SCK0 A/D AN7 converter ...
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Section 1 Overview TFP-100B, Type Symbol TFP-100G FP-100A TLP-113V I/O ports P17 100, P10 99 P27 89, P20 59 P35 P30 P47 ...
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TFP-100B, Type Symbol TFP-100G FP-100A TLP-113V I/O ports PF7 PF0 PG4 PG0 Notes: 1. Applies to the H8S/2319C F-ZTAT only. 2. Applies to the H8S/2319 F-ZTAT and H8S/2319C F-ZTAT only. 3. Only ...
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Section 1 Overview Rev.7.00 Feb. 14, 2007 page 26 of 1108 REJ09B0089-0700 ...
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Overview The H8S/2000 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2000 CPU has sixteen 16-bit general registers, can address a 16-Mbyte (4-Gbyte architecturally) linear ...
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Section 2 CPU • High-speed operation ⎯ All frequently-used instructions execute in one or two states ⎯ Maximum clock rate ⎯ 8/16/32-bit register-register add/subtract : 40 ns ⎯ 8 × 8-bit register-register multiply ⎯ 16 ÷ 8-bit register-register divide ⎯ ...
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Differences from H8/300 CPU In comparison to the H8/300 CPU, the H8S/2000 CPU has the following enhancements. • More general registers and control registers ⎯ Eight 16-bit expanded registers, and one 8-bit control register, have been added. • Expanded ...
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Section 2 CPU 2.2 CPU Operating Modes The H8S/2319 Group CPU has advanced operating mode. Advanced mode supports a maximum 16-Mbyte total address space (architecturally a maximum 16-Mbyte program area and a maximum of 4 Gbytes for program and data ...
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Exception Vector Table and Memory Indirect Branch Addresses: In advanced mode the top area starting at H'00000000 is allocated to the exception vector table in units of 32 bits. In each 32 bits, the upper 8 bits are ignored and ...
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Section 2 CPU Stack Structure: In advanced mode, when the program counter (PC) is pushed onto the stack in a subroutine call, and the PC, condition-code register (CCR), and extended control register (EXR) are pushed onto the stack in exception ...
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Address Space Figure 2.3 shows a memory map of the H8S/2000 CPU. The H8S/2000 CPU provides linear access to a maximum 16-Mbyte (4-Gbyte architecturally) address space in advanced mode. H'00000000 H'00FFFFFF H'FFFFFFFF Program area Cannot be used by the ...
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Section 2 CPU 2.4 Register Configuration 2.4.1 Overview The CPU has the internal registers shown in figure 2.4. There are two types of registers: general registers and control registers. General Registers (Rn) and Extended Registers (En) 15 ER0 ER1 ER2 ...
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General Registers The CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a data register, it can ...
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Section 2 CPU SP (ER7) 2.4.3 Control Registers The control registers are the 24-bit program counter (PC), 8-bit extended control register (EXR), and 8-bit condition-code register (CCR). (1) Program Counter (PC) This 24-bit counter indicates the address of the next ...
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Condition-Code Register (CCR) This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Bit 7—Interrupt Mask Bit (I): Masks interrupts other than ...
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Section 2 CPU Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC instructions. The and C flags are used as branching conditions for conditional branch (Bcc) instructions. 2.4.4 Initial Register ...
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General Register Data Formats Figure 2.7 shows the data formats in general registers. Data Type Register Number 1-bit data RnH 1-bit data RnL 4-bit BCD data RnH 4-bit BCD data RnL Byte data RnH Byte data RnL Figure 2.7 ...
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Section 2 CPU Data Type Register Number Word data Rn Word data En 15 MSB Longword data ERn 31 MSB En Legend: ERn: General register ER En: General register E Rn: General register R RnH: General register RH RnL: General ...
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Memory Data Formats Figure 2.8 shows the data formats in memory. The CPU can access word data and longword data in memory, but word or longword data must begin at an even address attempt is made to ...
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Section 2 CPU 2.6 Instruction Set 2.6.1 Overview The H8S/2000 CPU has 65 types of instructions. The instructions are classified by function in table 2.1. Table 2.1 Instruction Classification Function Instructions Data transfer MOV 1 POP * , PUSH * ...
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Instructions and Addressing Modes Table 2.2 indicates the combinations of instructions and addressing modes that the H8S/2600 CPU can use. Table 2.2 Combinations of Instructions and Addressing Modes Function Instruction MOV BWL BWL Data transfer ⎯ ⎯ POP, PUSH ...
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Section 2 CPU 2.6.3 Table of Instructions Classified by Function Table 2.3 summarizes the instructions in each functional category. The notation used in table 2.3 is defined below. Operation Notation General register (destination General register (source ...
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Table 2.3 Instructions Classified by Function Type Instruction Data transfer MOV MOVFPE MOVTPE POP PUSH LDM STM 1 Size * Function (EAs) → Rd, Rs → (Ead) B/W/L Moves data between two general registers or between a general register and ...
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Section 2 CPU Type Instruction Arithmetic ADD operations SUB ADDX SUBX INC DEC ADDS SUBS DAA DAS MULXU MULXS DIVXU Rev.7.00 Feb. 14, 2007 page 46 of 1108 REJ09B0089-0700 1 Size * Function Rd ± Rs → Rd, Rd ± ...
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Type Instruction Arithmetic DIVXS operations CMP NEG EXTU EXTS TAS 1 Size * Function Rd ÷ Rs → Rd B/W Performs signed division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit ...
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Section 2 CPU Type Instruction Logic AND operations OR XOR NOT Shift SHAL operations SHAR SHLL SHLR ROTL ROTR ROTXL ROTXR Rev.7.00 Feb. 14, 2007 page 48 of 1108 REJ09B0089-0700 1 Size * Function Rd ∧ Rs → Rd, Rd ...
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Type Instruction Bit- BSET manipulation instructions BCLR BNOT BTST BAND BIAND BOR BIOR 1 Size * Function 1 → (<bit-No.> of <EAd>) B Sets a specified bit in a general register or memory operand to 1. The bit number is ...
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Section 2 CPU Type Instruction Bit- BXOR manipulation instructions BIXOR BLD BILD BST BIST Rev.7.00 Feb. 14, 2007 page 50 of 1108 REJ09B0089-0700 1 Size * Function C ⊕ (<bit-No.> of <EAd>) → Exclusive-ORs the carry flag with ...
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Type Instruction Branch Bcc instructions JMP BSR JSR RTS Size Function — Branches to a specified relative address if a specified condition is true. The branching conditions are listed below. Mnemonic BRA(BT) BRN(BF) BHI BLS BCC(BHS) BCS(BLO) BNE BEQ BVC ...
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Section 2 CPU Type Instruction System control TRAPA instructions RTE SLEEP LDC STC ANDC ORC XORC NOP Rev.7.00 Feb. 14, 2007 page 52 of 1108 REJ09B0089-0700 1 Size * Function — Starts trap-instruction exception handling. — Returns from an exception-handling ...
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Type Instruction Block data EEPMOV.B transfer instruction EEPMOV.W Notes: 1. Size refers to the operand size. B: Byte W: Word L: Longword 2. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. Size Function ...
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Section 2 CPU 2.6.4 Basic Instruction Formats The CPU instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op field), a register field (r field), an effective address extension (EA field), and a condition field (cc). ...
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Addressing Modes and Effective Address Calculation 2.7.1 Addressing Mode The CPU supports the eight addressing modes listed in table 2.4. Each instruction uses a subset of these addressing modes. Arithmetic and logic instructions can use the register direct and ...
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Section 2 CPU (4) Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @-ERn: • Register indirect with post-increment—@ERn+ The register field of the instruction code specifies an address register (ERn) which contains the address of a memory operand. After the operand ...
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Immediate—#xx:8, #xx:16, or #xx:32: The instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand. The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit manipulation instructions contain 3-bit immediate data in ...
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Section 2 CPU If an odd address is specified in word or longword memory access branch address, the least significant bit is regarded as 0, causing data to be accessed or instruction code to be fetched at ...
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Table 2.6 Effective Address Calculation Section 2 CPU Rev.7.00 Feb. 14, 2007 page 59 of 1108 REJ09B0089-0700 ...
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Section 2 CPU Rev.7.00 Feb. 14, 2007 page 60 of 1108 REJ09B0089-0700 ...
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Section 2 CPU Rev.7.00 Feb. 14, 2007 page 61 of 1108 REJ09B0089-0700 ...
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Section 2 CPU 2.8 Processing States 2.8.1 Overview The CPU has five main processing states: the reset state, exception handling state, program execution state, bus-released state, and power-down state. Figure 2.11 shows a diagram of the processing states. Figure 2.12 ...
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End of bus request Bus-released state End of exception handling Exception-handling state RES = high *1 Reset state From any state except hardware standby mode, a transition to the reset state occurs whenever RES Notes: 1. goes low. A transition ...
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Section 2 CPU 2.8.3 Exception-Handling State The exception-handling state is a transient state that occurs when the CPU alters the normal processing flow due to a reset, interrupt, or trap instruction. The CPU fetches a start address (vector) from the ...
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Reset Exception Handling After the RES pin has gone low and the reset state has been entered, when RES goes high again, reset exception handling starts. When reset exception handling starts the CPU fetches a start address (vector) from ...
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Section 2 CPU Advanced mode SP CCR PC (24 bits) (c) Interrupt control mode 0 Note: * Ignored when returning. Figure 2.13 Stack Structure after Exception Handling (Examples) 2.8.4 Program Execution State In this state the CPU executes program instructions ...
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Module stop mode permits halting of the operation of individual modules, other than the CPU. For details, refer to section 19, Power-Down Modes. (1) Sleep Mode: A transition to sleep mode is made ...
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Section 2 CPU φ Internal address bus Internal read signal Read access Internal data bus Internal write signal Write access Internal data bus Figure 2.14 On-Chip Memory Access Cycle φ Address bus AS RD HWR, LWR Data bus Figure 2.15 ...
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On-Chip Supporting Module Access Timing The on-chip supporting modules are accessed in two states. The data bus is either 8 bits or 16 bits wide, depending on the particular internal I/O register being accessed. Figure 2.16 shows the access ...
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Section 2 CPU φ Address bus AS RD HWR, LWR Data bus Figure 2.17 Pin States during On-Chip Supporting Module Access 2.9.4 External Address Space Access Timing The external address space is accessed with an 8-bit or 16-bit data bus ...
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Section 3 MCU Operating Modes 3.1 Overview 3.1.1 Operating Mode Selection (H8S/2318 F-ZTAT, H8S/2317 F-ZTAT, H8S/2315 F-ZTAT, and H8S/2314 F-ZTAT) The H8S/2318 F-ZTAT, H8S/2317 F-ZTAT, H8S/2315 F-ZTAT, and H8S/2314 F-ZTAT have eight operating modes (modes 10, 11, ...
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Section 3 MCU Operating Modes The CPU's architecture allows for 4 Gbytes of address space, but the H8S/2318 F-ZTAT, H8S/2317 F-ZTAT, H8S/2315 F-ZTAT, and H8S/2314 F-ZTAT actually access a maximum of 16 Mbytes. Modes are externally expanded ...
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Table 3.2 MCU Operating Mode Selection (Mask ROM, ROMless versions, H8S/2319 F- ZTAT, and H8S/2319C F-ZTAT) MCU Operating MD2 MD1 MD0 Mode ...
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Section 3 MCU Operating Modes only be used in modes This means that the mode pins must be set to select one of these modes. Do not change the inputs at the mode pins during operation. 3.1.3 ...
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Bits 2 to 0—Mode Select (MDS2 to MDS0): These bits indicate the input levels at pins MD2 to MD0 (the current operating mode). Bits MDS2 to MDS0 correspond to pins MD2 to MD0. MDS2 to MDS0 are ...
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Section 3 MCU Operating Modes Bit 2—LWR Output Disable (LWROD): Enables or disables LWR output. Bit 2 LWROD Description PF3 is designated as LWR output pin 0 PF3 is designated as I/O port, and does not function as LWR output ...
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Bit 3 FLSHE Description 0 H8S/2319 F-ZTAT, H8S/2318 F-ZTAT, H8S/2317 F-ZTAT, H8S/2315 F-ZTAT, and H8S/2314 F-ZTAT • Flash control registers are not selected for addresses H'FFFFC8 to H'FFFFCB H8S/2319C F-ZTAT • Flash control registers are not selected for addresses H'FFFFC4 ...
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Section 3 MCU Operating Modes 3.3.3 Mode 3 (H8S/2319 F-ZTAT and H8S/2319C F-ZTAT Only) This is a flash memory boot mode. See section 17, ROM, for details. Except for the fact that flash memory programming and erasing can be performed, ...
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Mode 6 (Expanded Mode with On-Chip ROM Enabled) The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled. Pins P13 to P10, ports A, B, and C function as input ports immediately after ...
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Section 3 MCU Operating Modes 3.3.11 Modes 12 and 13 Modes 12 and 13 are not supported in the H8S/2319 Group, and must not be set. 3.3.12 Mode 14 (H8S/2318 F-ZTAT, H8S/2317 F-ZTAT, H8S/2315 F-ZTAT, and H8S/2314 F-ZTAT Only) This ...
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Table 3.4 Pin Functions in Each Mode Port Mode Port 1 P13 to P10 /T/A Port A PA3 to PA0 A Port B A Port C A Port D D P/D * Port E P/C * ...
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Section 3 MCU Operating Modes Mode 2 Boot Mode (advanced expanded mode with on-chip ROM enabled) H'000000 H'010000 external address H'080000 External address H'FF7400 Reserved area H'FFDC00 On-chip RAM H'FFFC00 External address H'FFFE50 H'FFFF08 External address H'FFFF28 H'FFFFFF Notes: 1. ...
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Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000 External address space H'080000 External address space H'FF7400 *4 Reserved area H'FFDC00 *3 On-chip RAM H'FFFC00 External address space H'FFFE50 Internal I/O registers H'FFFF08 External address space H'FFFF28 ...
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Section 3 MCU Operating Modes Mode 1 User Boot Mode (advanced single-chip mode) H'000000 On-chip ROM On-chip ROM/ reserved *2 *4 area H'080000 *4 Reserved area H'0FFFFF H'FF7400 *4 Reserved area H'FFBC00 *3 On-chip RAM H'FFFBFF H'FFFE50 Internal I/O registers ...
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Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000 External address space H'FF7400 *4 Reserved area H'FFBC00 *3 On-chip RAM H'FFFC00 External address space H'FFFE50 Internal I/O registers H'FFFF08 External address space H'FFFF28 Internal I/O registers H'FFFFFF ...
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Section 3 MCU Operating Modes *1 Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000 External address space H'FFDC00 *4 On-chip RAM External address H'FFFC00 space H'FFFE50 Internal I/O registers H'FFFF08 External address space H'FFFF28 Internal I/O ...
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Mode 10 Boot Mode (advanced expanded mode with on-chip ROM enabled) H'000000 On-chip ROM H'010000 On-chip ROM/ external address space H'040000 External address space H'FFDC00 On-chip RAM External address H'FFFC00 space H'FFFE50 Internal I/O registers H'FFFF08 External address space H'FFFF28 ...
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Section 3 MCU Operating Modes Mode 14 User Program Mode (advanced expanded mode with on-chip ROM enabled) H'000000 On-chip ROM H'010000 On-chip ROM/ external address H'040000 External address H'FFDC00 On-chip RAM External address H'FFFC00 H'FFFE50 H'FFFF08 External address H'FFFF28 H'FFFFFF ...
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Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000 External address space H'FFDC00 *3 On-chip RAM External address H'FFFC00 space H'FFFE50 Internal I/O registers H'FFFF08 External address space H'FFFF28 Internal I/O registers H'FFFFFF Notes: 1. External addresses ...
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Section 3 MCU Operating Modes Mode 10 Boot Mode (advanced expanded mode with on-chip ROM enabled) H'000000 H'010000 H'020000 H'040000 H'FFDC00 H'FFFC00 H'FFFE50 H'FFFF08 H'FFFF28 H'FFFFFF Notes: 1. External addresses when EAE = 1 in BCRL; on-chip ROM or reserved ...
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Mode 14 Boot Mode (advanced expanded mode with on-chip ROM enabled) H'000000 On-chip ROM H'010000 On-chip ROM/ external address H'020000 Reserved area external address H'040000 External address H'FFDC00 On-chip RAM External address H'FFFC00 H'FFFE50 I/O registers H'FFFF08 External address H'FFFF28 ...
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Section 3 MCU Operating Modes Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000 External address space H'FFDC00 *2 On-chip RAM External address H'FFFC00 space H'FFFE50 Internal I/O registers H'FFFF08 External address space H'FFFF28 Internal I/O registers ...
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Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000 External address space H'060000 *4 Reserved area H'080000 External address space H'FFDC00 *3 On-chip RAM H'FFFC00 External address space H'FFFE50 Internal I/O registers H'FFFF08 External address space H'FFFF28 ...
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Section 3 MCU Operating Modes Mode 10 Boot Mode (advanced expanded mode with on-chip ROM enabled) H'000000 On-chip ROM H'010000 On-chip ROM/ external address H'060000 Reserved area H'080000 External address H'FFDC00 On-chip RAM H'FFFC00 External address H'FFFE50 H'FFFF08 External address ...
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Mode 14 User Program Mode (advanced expanded mode with on-chip ROM enabled) H'000000 On-chip ROM H'010000 On-chip ROM/ external address H'060000 Reserved area H'080000 External address H'FFDC00 On-chip RAM H'FFFC00 External address H'FFFE50 I/O registers H'FFFF08 External address H'FFFF28 I/O ...
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Section 3 MCU Operating Modes Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000 External address space H'060000 *4 Reserved area H'080000 External address space H'FFDC00 *5 Reserved area H'FFEC00 *3 On-chip RAM H'FFFC00 External address space ...
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Mode 10 Boot Mode (advanced expanded mode with on-chip ROM enabled) H'000000 On-chip ROM H'010000 On-chip ROM/ external address H'060000 Reserved area H'080000 External address H'FFDC00 Reserved area H'FFEC00 On-chip RAM H'FFFC00 External address H'FFFE50 I/O registers H'FFFF08 External address ...
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Section 3 MCU Operating Modes Mode 14 User Program Mode (advanced expanded mode with on-chip ROM enabled) H'000000 On-chip ROM H'010000 On-chip ROM/ external address H'060000 Reserved area H'080000 External address H'FFDC00 Reserved area H'FFEC00 On-chip RAM H'FFFC00 External address ...
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Section 4 Exception Handling 4.1 Overview 4.1.1 Exception Handling Types and Priority As table 4.1 indicates, exception handling may be caused by a reset, trap instruction, or interrupt. Exception handling is prioritized as shown in table 4.1. If two or ...
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Section 4 Exception Handling 4.1.2 Exception Handling Operation Exceptions originate from various sources. Trap instructions and interrupts are handled as follows: 1. The program counter (PC), condition code register (CCR), and extend register (EXR) are pushed onto the stack. 2. ...
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Table 4.2 Exception Vector Table Exception Source Reset Reserved Reserved for system use Trace Reserved for system use External interrupt NMI Trap instruction (4 sources) Reserved for system use External interrupt IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 2 ...
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Section 4 Exception Handling 4.2 Reset 4.2.1 Overview A reset has the highest exception priority. When the RES pin goes low, all processing halts and the chip enters the reset state. A reset initializes the internal state of the CPU ...
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RES Address bus RD HWR, LWR (1), (3) Reset exception handling vector address ((1) = H'000000, (3) = H'000002) (2), (4) Start address (contents of reset exception vector address) (5) Start address ((5) = ...
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Section 4 Exception Handling 4.3 Traces Traces are enabled in interrupt control mode 2. Trace mode is not activated in interrupt control mode 0, irrespective of the state of the T bit. For details of interrupt control modes, see section ...
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Interrupts Interrupt exception handling can be requested by nine external sources (NMI, IRQ7 to IRQ0) and 43 internal sources in the on-chip supporting modules. Figure 4.3 classifies the interrupt sources and the number of interrupts of each type. The ...
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Section 4 Exception Handling 4.5 Trap Instruction Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction exception handling can be executed at all times in the program execution state. The TRAPA instruction fetches a start address ...
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Notes on Use of the Stack When accessing word data or longword data, the chip assumes that the lowest address bit is 0. The stack should always be accessed by word transfer instruction or longword transfer instruction, and the ...
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Section 4 Exception Handling Rev.7.00 Feb. 14, 2007 page 108 of 1108 REJ09B0089-0700 ...
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Section 5 Interrupt Controller 5.1 Overview 5.1.1 Features The chip controls interrupts by means of an interrupt controller. The interrupt controller has the following features. The available interrupt sources are external interrupts (NMI, IRQ7 to IRQ0) and internal interrupts (43 ...
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Section 5 Interrupt Controller 5.1.2 Block Diagram A block diagram of the interrupt controller is shown in figure 5.1. INTM1 INTM0 SYSCR NMIEG NMI input NMI input unit IRQ input unit IRQ input ISCR Internal interrupt request SWDTEND to TEI ...
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Pin Configuration Table 5.1 summarizes the pins of the interrupt controller. Table 5.1 Interrupt Controller Pins Name Symbol Nonmaskable interrupt NMI IRQ7 to IRQ0 Input External interrupt requests 5.1.4 Register Configuration Table 5.2 summarizes the registers ...
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Section 5 Interrupt Controller 5.2 Register Descriptions 5.2.1 System Control Register (SYSCR) Bit : 7 — Initial value : 0 R/W : R/W SYSCR is an 8-bit readable/writable register that selects the interrupt control mode, and the detected edge for ...
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Interrupt Priority Registers (IPRA to IPRK) Bit : 7 — Initial value : 0 R/W : — The IPR registers are eleven 8-bit readable/writable registers that set priorities (levels for interrupts other than ...
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Section 5 Interrupt Controller As shown in table 5.3, multiple interrupts are assigned to one IPR. Setting a value in the range from H'0 to H'7 in the 3-bit groups of bits and sets ...
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IRQ Sense Control Registers H and L (ISCRH, ISCRL) ISCRH Bit : 15 IRQ7SCB IRQ7SCA IRQ6SCB IRQ6SCA IRQ5SCB IRQ5SCA IRQ4SCB IRQ4SCA Initial value : 0 R/W : R/W ISCRL Bit : 7 IRQ3SCB IRQ3SCA IRQ2SCB IRQ2SCA IRQ1SCB IRQ1SCA IRQ0SCB ...
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Section 5 Interrupt Controller 5.2.5 IRQ Status Register (ISR) Bit : 7 IRQ7F IRQ6F Initial value : 0 R/(W) * R/(W) * R/W : Note: * Only 0 can be written, to clear the flag. ISR is an 8-bit readable/writable ...
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Interrupt Sources Interrupt sources comprise external interrupts (NMI and IRQ7 to IRQ0) and internal interrupts (43 sources). 5.3.1 External Interrupts There are nine external interrupts: NMI and IRQ7 to IRQ0. NMI and IRQ7 to IRQ0 can be used to ...
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Section 5 Interrupt Controller Figure 5.3 shows the timing of setting IRQnF. φ IRQn input pin IRQnF The vector numbers for IRQ7 to IRQ0 interrupt exception handling are 23 to 16. Detection of IRQ7 to IRQ0 interrupts does not depend ...
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Table 5.4 Interrupt Sources, Vector Addresses, and Interrupt Priorities Origin of Interrupt Interrupt Source Source Power-on reset Reserved Reserved for system use Trace Reserved for system use NMI External pin Trap instruction (4 sources) Reserved for system use IRQ0 External ...
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Section 5 Interrupt Controller Origin of Interrupt Interrupt Source Source SWDTEND (software- DTC activated data transfer end) WOVI (interval timer) Watchdog timer 25 Reserved — Reserved — ADI (A/D conversion A/D end) Reserved — TGI0A (TGR0A input TPU capture/compare channel ...
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Origin of Interrupt Interrupt Source Source TGI1A (TGR1A input TPU capture/compare channel 1 match) TGI1B (TGR1B input capture/compare match) TCI1V (overflow 1) TCI1U (underflow 1) TGI2A (TGR2A input TPU capture/compare channel 2 match) TGI2B (TGR2B input capture/compare match) TCI2V (overflow ...
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Section 5 Interrupt Controller Origin of Interrupt Interrupt Source Source TGI4A (TGR4A input TPU capture/compare channel 4 match) TGI4B (TGR4B input capture/compare match) TCI4V (overflow 4) TCI4U (underflow 4) TGI5A (TGR5A input TPU capture/compare channel 5 match) TGI5B (TGR5B input ...
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Origin of Interrupt Interrupt Source Source Reserved — ERI0 (receive error 0) SCI channel 0 RXI0 (receive-data-full 0) TXI0 (transmit-data- empty 0) TEI0 (transmit end 0) ERI1 (receive error 1) SCI channel 1 RXI1 (receive-data-full 1) TXI1 (transmit-data- empty 1) ...
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Section 5 Interrupt Controller 5.4 Interrupt Operation 5.4.1 Interrupt Control Modes and Interrupt Operation Interrupt operations in the chip differ depending on the interrupt control mode. NMI interrupts are accepted at all times except in the reset state and the ...
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Figure 5.4 shows a block diagram of the priority decision circuit. Interrupt source Figure 5.4 Block Diagram of Interrupt Control Operation Interrupt Acceptance Control: In interrupt control mode 0, interrupt acceptance is controlled by the I bit in CCR. Table ...
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Section 5 Interrupt Controller 8-Level Control: In interrupt control mode 2, 8-level mask level determination is performed for the selected interrupts in interrupt acceptance control according to the interrupt priority level (IPR). The interrupt source selected is the interrupt with ...
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Interrupt Control Mode 0 Enabling and disabling of IRQ interrupts and on-chip supporting module interrupts can be set by means of the I bit in the CPU’s CCR. Interrupts are enabled when the I bit is cleared to 0, ...
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Section 5 Interrupt Controller IRQ0? Yes Figure 5.5 Flowchart of Procedure Up to Interrupt Acceptance in Rev.7.00 Feb. 14, 2007 page 128 of 1108 REJ09B0089-0700 Program execution state Interrupt generated? Yes Yes NMI Yes No IRQ1? ...
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Interrupt Control Mode 2 Eight-level masking is implemented for IRQ interrupts and on-chip supporting module interrupts by comparing the interrupt mask level set by bits EXR in the CPU with IPR. Figure 5.6 shows a ...
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Section 5 Interrupt Controller Level 7 interrupt? Yes Mask level 6 or below? Yes Figure 5.6 Flowchart of Procedure Up to Interrupt Acceptance in Rev.7.00 Feb. 14, 2007 page 130 of 1108 REJ09B0089-0700 Program execution state No Interrupt generated? Yes ...
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Interrupt Exception Handling Sequence Figure 5.7 shows the interrupt exception handling sequence. The example shown is for the case where interrupt control mode 0 is set in advanced mode, and the program area and stack area are in on-chip ...
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Section 5 Interrupt Controller Figure 5.7 Interrupt Exception Handling Rev.7.00 Feb. 14, 2007 page 132 of 1108 REJ09B0089-0700 ...
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Interrupt Response Times The chip is capable of fast word transfer instruction to on-chip memory, and the program area is provided in on-chip ROM and the stack area in on-chip RAM, enabling high-speed processing. Table 5.9 shows interrupt response ...
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Section 5 Interrupt Controller 5.5 Usage Notes 5.5.1 Contention between Interrupt Generation and Disabling When an interrupt enable bit is cleared disable interrupts, the disabling becomes effective after execution of the instruction. In other words, when an ...
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The above contention will not occur if an enable bit or interrupt source flag is cleared to 0 while the interrupt is masked. 5.5.2 Instructions that Disable Interrupts Instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any ...
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Section 5 Interrupt Controller 5.6 DTC Activation by Interrupt 5.6.1 Overview The DTC can be activated by an interrupt. In this case, the following options are available. 1. Interrupt request to CPU 2. Activation request to DTC 3. Selection of ...
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Operation The interrupt controller has three main functions in DTC control. Selection of Interrupt Source: For interrupt sources possible to select DTC activation request or CPU interrupt request with the DTCE bit of DTCERA to DTCERE in ...
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Section 5 Interrupt Controller Usage Note: SCI and A/D converter interrupt sources are cleared when the DTC reads or writes to the prescribed register, and are not dependent upon the DTA bit or DISEL bit. Rev.7.00 Feb. 14, 2007 page ...
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Section 6 Bus Controller 6.1 Overview The chip has a built-in bus controller (BSC) that manages the external address space divided into eight areas. The bus specifications, such as bus width and number of access states, can be set independently ...
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Section 6 Bus Controller 6.1.2 Block Diagram Figure 6.1 shows a block diagram of the bus controller. CS0 to CS7 External bus control signals BREQ BACK BREQO WAIT Figure 6.1 Block Diagram of Bus Controller Rev.7.00 Feb. 14, 2007 page ...
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Pin Configuration Table 6.1 summarizes the pins of the bus controller. Table 6.1 Bus Controller Pins Name Symbol AS Address strobe RD Read HWR High write LWR Low write CS0 Chip select 0 CS1 Chip select 1 CS2 Chip ...
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Section 6 Bus Controller 6.1.4 Register Configuration Table 6.2 summarizes the registers of the bus controller. Table 6.2 Bus Controller Registers Name Bus width control register Access state control register Wait control register H Wait control register L Bus control ...
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Register Descriptions 6.2.1 Bus Width Control Register (ABWCR) Bit : 7 ABW7 ABW6 Modes Initial value : 1 R/W : R/W Mode 4 Initial value : 0 R/W : R/W ABWCR is an 8-bit readable/writable register ...
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Section 6 Bus Controller 6.2.2 Access State Control Register (ASTCR) Bit : 7 AST7 AST6 Initial value : 1 R/W : R/W ASTCR is an 8-bit readable/writable register that designates each area as either a 2-state access space or a ...
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Wait Control Registers H and L (WCRH, WCRL) WCRH and WCRL are 8-bit readable/writable registers that select the number of program wait states for each area. Program waits are not inserted in the case of on-chip memory or internal ...
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Section 6 Bus Controller Bits 5 and 4—Area 6 Wait Control 1 and 0 (W61, W60): These bits select the number of program wait states when area 6 in external space is accessed while the AST6 bit in ASTCR is ...
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WCRL Bit : 7 W31 Initial value : 1 R/W : R/W Bits 7 and 6—Area 3 Wait Control 1 and 0 (W31, W30): These bits select the number of program wait states when area 3 in external space is ...
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Section 6 Bus Controller Bits 3 and 2—Area 1 Wait Control 1 and 0 (W11, W10): These bits select the number of program wait states when area 1 in external space is accessed while the AST1 bit in ASTCR is ...
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Bit 7—Idle Cycle Insert 1 (ICIS1): Selects whether or not one idle cycle state inserted between bus cycles when successive external read cycles are performed in different areas. Bit 7 ICIS1 Description 0 Idle cycle not inserted ...
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Section 6 Bus Controller Bit 3—Burst Cycle Select 0 (BRSTS0): Selects the number of words that can be accessed in a burst ROM interface burst access. Bit 3 BRSTS0 Description 0 Max. 4 words in burst access 1 Max. 8 ...
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Bit 6—BREQO Pin Enable (BREQOE): Outputs a signal that requests the external bus master to drop the bus request signal (BREQ) in the external bus release state, when an internal bus master performs an external space access. Bit 6 BREQOE ...
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Section 6 Bus Controller 6.3 Overview of Bus Control 6.3.1 Area Partitioning In advanced mode, the bus controller partitions the 16-Mbyte address space into eight areas 2-Mbyte units, and performs bus control for external space in ...
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Bus Specifications The external space bus specifications consist of three elements: bus width, number of access states, and number of program wait states. The bus width and number of access states for on-chip memory and internal I/O registers are ...
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Section 6 Bus Controller Table 6.3 Bus Specifications for Each Area (Basic Bus Interface) WCRH, WCRL ABWCR ASTCR ABWn ASTn Wn1 0 0 — — 6.3.3 Memory Interfaces The chip’s memory interfaces ...
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Advanced Mode The initial state of each area is basic bus interface, 3-state access space. The initial bus width is selected according to the operating mode. The bus specifications described here cover basic items only, and the sections on ...
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Section 6 Bus Controller 6.3.5 Chip Select Signals The chip can output chip select signals (CS0 to CS7) to areas the signal being driven low when the corresponding external space area is accessed. Figure 6.3 shows an ...
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Basic Bus Interface 6.4.1 Overview The basic bus interface enables direct connection of ROM, SRAM, and so on. The bus specifications can be selected with ABWCR, ASTCR, WCRH, and WCRL (see table 6.3). 6.4.2 Data Size and Data Alignment ...
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Section 6 Bus Controller 16-Bit Access Space: Figure 6.5 illustrates data alignment control for the 16-bit access space. With the 16-bit access space, the upper data bus (D for accesses. The amount of data that can be accessed at one ...
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Valid Strobes Table 6.4 shows the data buses used and valid strobes for the access spaces read, the RD signal is valid without discrimination between the upper and lower halves of the data bus write, ...
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Section 6 Bus Controller 6.4.4 Basic Timing 8-Bit 2-State Access Space: Figure 6.6 shows the bus timing for an 8-bit 2-state access space. When an 8-bit access space is accessed, the upper half (D The LWR pin is fixed high. ...
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Access Space: Figure 6.7 shows the bus timing for an 8-bit 3-state access space. When an 8-bit access space is accessed, the upper half (D The LWR pin is fixed high. Wait states can be inserted. φ Address ...
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Section 6 Bus Controller 16-Bit 2-State Access Space: Figures 6.8 to 6.10 show bus timings for a 16-bit 2-state access space. When a 16-bit access space is accessed, the upper half (D for the even address, and the lower half ...
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Address bus CSn Read HWR LWR Write Note Figure 6.9 Bus Timing ...
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Section 6 Bus Controller φ Address bus CSn Read HWR LWR Write Note Figure 6.10 Bus Timing for 16-Bit ...
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Access Space: Figures 6.11 to 6.13 show bus timings for a 16-bit 3-state access space. When a 16-bit access space is accessed, the upper half (D for the even address, and the lower half (D Wait states can ...
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Section 6 Bus Controller φ Address bus CSn Read HWR LWR Write Note ...